NXP Semiconductors
LPC5410x
2024.06.02
LPC5410x Cortex-M4 MCU; Cortex-M0+ coprocessor
CM4
r0p0
little
true
true
3
false
8
32
ADC0
12-bit ADC controller 0
ADC0
0x0
0x0
0x1000
registers
n
ADC_SEQA
26
ADC_SEQB
27
ADC_THCMP
28
CALIB
ADC Calibration Register.
0x70
read-write
n
0x0
0x0
CALIB
Calibration request. Setting this bit will launch an ADC calibration cycle. This bit can only be set to a 1 by software. It is cleared automatically when the calibration cycle completes.
0
1
CALREQD
Calibration required. This read-only bit indicates if calibration is required when enabling the ADC. CALREQD will be 1 if no calibration has been run since the chip was powered-up and if the BYPASSCAL bit in the ADCTRL register is low. The ADC API will test this bit to determine whether to initiate a calibration cycle or whether to set the ADC_INIT bit (in the ADSTARTUP register) to launch the ADC initialization process which includes a dummy conversion cycle. Note: A dummy conversion cycle requires approximately 6 ADC clocks as opposed to 81 clocks required for calibration.
1
2
CALVALUE
Calibration Value. This read-only field displays the calibration value established during last calibration cycle. This value is not typically of any use to the user.
2
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
32
CHAN_THRSEL
ADC Channel-Threshold Select Register. Specifies which set of threshold compare registers are to be used for each channel
0x60
read-write
n
0x0
0x0
CH0_THRSEL
Threshold select for channel 0.
0
1
ENUM
THRESHOLD0
Threshold 0. Results for this channel will be
compared against the threshold levels indicated in the
THR0_LOW and THR0_HIGH registers.
0
THRESHOLD1
Threshold 1. Results for this channel will be
compared against the threshold levels indicated in the
THR1_LOW and THR1_HIGH registers.
1
CH10_THRSEL
Threshold select for channel 10. See description for channel 0.
10
11
CH11_THRSEL
Threshold select for channel 11. See description for channel 0.
11
12
CH1_THRSEL
Threshold select for channel 1. See description for channel 0.
1
2
CH2_THRSEL
Threshold select for channel 2. See description for channel 0.
2
3
CH3_THRSEL
Threshold select for channel 3. See description for channel 0.
3
4
CH4_THRSEL
Threshold select for channel 4. See description for channel 0.
4
5
CH5_THRSEL
Threshold select for channel 5. See description for channel 0.
5
6
CH6_THRSEL
Threshold select for channel 6. See description for channel 0.
6
7
CH7_THRSEL
Threshold select for channel 7. See description for channel 0.
7
8
CH8_THRSEL
Threshold select for channel 8. See description for channel 0.
8
9
CH9_THRSEL
Threshold select for channel 9. See description for channel 0.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
CTRL
ADC Control Register. Contains the clock divide value, enable bits for each sequence and the ADC power-down bit.
0x0
read-write
n
0x0
0x0
ASYNMODE
Select clock mode.
8
9
ENUM
SYNCHRONOUS_MODE
Synchronous mode. The ADC clock is derived from the
system clock based on the divide value selected in the
CLKDIV field. The ADC clock will be started in a controlled
fashion in response to a trigger to eliminate any
uncertainty in the launching of an ADC conversion in
response to any synchronous (on-chip) trigger. In
Synchronous mode with the SYNCBYPASS bit (in a sequence
control register) set, sampling of the ADC input and start
of conversion will initiate 2 system clocks after the
leading edge of a (synchronous) trigger pulse.
0
ASYNCHRONOUS_MODE
Asynchronous mode. The ADC clock is based on the
output of the ADC clock divider ADCCLKSEL in the SYSCON
block.
1
BYPASSCAL
Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application.
11
12
ENUM
CALIBRATE
Calibrate. The stored calibration value will be
applied to the ADC during conversions to compensated for
offset error. A calibration cycle must be performed each
time the chip is powered-up. Re-calibration may be warranted
periodically - especially if operating conditions have
changed.
0
BYPASS_CALIBRATION
Bypass calibration. Calibration is not utilized.
Less time is required when enabling the ADC - particularly
following chip power-up. Attempts to launch a calibration
cycle are blocked when this bit is set.
1
CLKDIV
In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 80 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode.
0
8
RESOL
The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion requires the selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution
9
11
ENUM
6_BIT_RESOLUTION
6-bit resolution. An ADC conversion requires 9 ADC
clocks, plus any clocks specified by the TSAMP
field.
0x0
8_BIT_RESOLUTION
8-bit resolution. An ADC conversion requires 11 ADC
clocks, plus any clocks specified by the TSAMP
field.
0x1
10_BIT_RESOLUTION
10-bit resolution. An ADC conversion requires 13
ADC clocks, plus any clocks specified by the TSAMP
field.
0x2
12_BIT_RESOLUTION
12-bit resolution. An ADC conversion requires 15
ADC clocks, plus any clocks specified by the TSAMP
field.
0x3
TSAMP
Sample Time. The default sampling period (TSAMP = 000) at the start of each conversion is 2.5 ADC clock periods. Depending on a variety of factors, including operating conditions and the output impedance of the analog source, longer sampling times may be required. The TSAMP field specifies the number of additional ADC clock cycles, from zero to seven, by which the sample period will be extended. The total conversion time will increase by the same number of clocks. 000 - The sample period will be the default 2.5 ADC clocks. A complete conversion with 12-bits of accuracy will require 15 clocks. 001- The sample period will be extended by one ADC clock to a total of 3.5 clock periods. A complete 12-bit conversion will require 16 clocks. 010 - The sample period will be extended by two clocks to 4.5 ADC clock cycles. A complete 12-bit conversion will require 17 ADC clocks. : 111 - The sample period will be extended by two clocks to 9.5 ADC clock cycles. A complete 12-bit conversion will require 22 ADC clocks.
12
15
DAT0
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x40
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT1
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x64
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT10
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x25C
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT11
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x2A8
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT2
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x8C
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT3
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0xB8
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT4
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0xE8
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT5
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x11C
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT6
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x154
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT7
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x190
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT8
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x1D0
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
DAT9
ADC Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.
0x214
read-only
n
0x0
0x0
CHANNEL
This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)
26
30
DATAVALID
This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
31
32
OVERRUN
This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
4
16
THCMPCROSS
Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
18
20
THCMPRANGE
Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved.
16
18
FLAGS
ADC Flags Register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).
0x68
read-only
n
0x0
0x0
OVERRUN0
Mirrors the OVERRRUN status flag from the result register for ADC channel 0
12
13
OVERRUN1
Mirrors the OVERRRUN status flag from the result register for ADC channel 1
13
14
OVERRUN10
Mirrors the OVERRRUN status flag from the result register for ADC channel 10
22
23
OVERRUN11
Mirrors the OVERRRUN status flag from the result register for ADC channel 11
23
24
OVERRUN2
Mirrors the OVERRRUN status flag from the result register for ADC channel 2
14
15
OVERRUN3
Mirrors the OVERRRUN status flag from the result register for ADC channel 3
15
16
OVERRUN4
Mirrors the OVERRRUN status flag from the result register for ADC channel 4
16
17
OVERRUN5
Mirrors the OVERRRUN status flag from the result register for ADC channel 5
17
18
OVERRUN6
Mirrors the OVERRRUN status flag from the result register for ADC channel 6
18
19
OVERRUN7
Mirrors the OVERRRUN status flag from the result register for ADC channel 7
19
20
OVERRUN8
Mirrors the OVERRRUN status flag from the result register for ADC channel 8
20
21
OVERRUN9
Mirrors the OVERRRUN status flag from the result register for ADC channel 9
21
22
OVR_INT
Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers.
31
32
RESERVED
Reserved.
26
28
SEQA_INT
Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register.
28
29
SEQA_OVR
Mirrors the global OVERRUN status flag in the SEQA_GDAT register
24
25
SEQB_INT
Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register.
29
30
SEQB_OVR
Mirrors the global OVERRUN status flag in the SEQB_GDAT register
25
26
THCMP0
Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1.
0
1
THCMP1
Threshold comparison event on Channel 1. See description for channel 0.
1
2
THCMP10
Threshold comparison event on Channel 10. See description for channel 0.
10
11
THCMP11
Threshold comparison event on Channel 11. See description for channel 0.
11
12
THCMP2
Threshold comparison event on Channel 2. See description for channel 0.
2
3
THCMP3
Threshold comparison event on Channel 3. See description for channel 0.
3
4
THCMP4
Threshold comparison event on Channel 4. See description for channel 0.
4
5
THCMP5
Threshold comparison event on Channel 5. See description for channel 0.
5
6
THCMP6
Threshold comparison event on Channel 6. See description for channel 0.
6
7
THCMP7
Threshold comparison event on Channel 7. See description for channel 0.
7
8
THCMP8
Threshold comparison event on Channel 8. See description for channel 0.
8
9
THCMP9
Threshold comparison event on Channel 9. See description for channel 0.
9
10
THCMP_INT
Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits.
30
31
INTEN
ADC Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.
0x64
read-write
n
0x0
0x0
ADCMPINTEN0
Threshold comparison interrupt enable for channel 0.
3
5
ENUM
DISABLED
Disabled.
0x0
OUTSIDE_THRESHOLD
Outside threshold.
0x1
CROSSING_THRESHOLD
Crossing threshold.
0x2
RESERVED
Reserved
0x3
ADCMPINTEN1
Channel 1 threshold comparison interrupt enable. See description for channel 0.
5
7
ADCMPINTEN10
Channel 10 threshold comparison interrupt enable. See description for channel 0.
23
25
ADCMPINTEN11
Channel 21 threshold comparison interrupt enable. See description for channel 0.
25
27
ADCMPINTEN2
Channel 2 threshold comparison interrupt enable. See description for channel 0.
7
9
ADCMPINTEN3
Channel 3 threshold comparison interrupt enable. See description for channel 0.
9
11
ADCMPINTEN4
Channel 4 threshold comparison interrupt enable. See description for channel 0.
11
13
ADCMPINTEN5
Channel 5 threshold comparison interrupt enable. See description for channel 0.
13
15
ADCMPINTEN6
Channel 6 threshold comparison interrupt enable. See description for channel 0.
15
17
ADCMPINTEN7
Channel 7 threshold comparison interrupt enable. See description for channel 0.
17
19
ADCMPINTEN8
Channel 8 threshold comparison interrupt enable. See description for channel 0.
19
21
ADCMPINTEN9
Channel 9 threshold comparison interrupt enable. See description for channel 0.
21
23
OVR_INTEN
Overrun interrupt enable.
2
3
ENUM
DISABLED
Disabled. The overrun interrupt is
disabled.
0
ENABLED
Enabled. The overrun interrupt is enabled.
Detection of an overrun condition on any of the 12 channel
data registers will cause an overrun interrupt/DMA trigger.
In addition, if the MODE bit for a particular sequence is 0,
then an overrun in the global data register for that
sequence will also cause this interrupt/DMA trigger to be
asserted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
27
32
SEQA_INTEN
Sequence A interrupt enable.
0
1
ENUM
DISABLED
Disabled. The sequence A interrupt/DMA trigger is
disabled.
0
ENABLED
Enabled. The sequence A interrupt/DMA trigger is
enabled and will be asserted either upon completion of each
individual conversion performed as part of sequence A, or
upon completion of the entire A sequence of conversions,
depending on the MODE bit in the SEQA_CTRL
register.
1
SEQB_INTEN
Sequence B interrupt enable.
1
2
ENUM
DISABLED
Disabled. The sequence B interrupt/DMA trigger is
disabled.
0
ENABLED
Enabled. The sequence B interrupt/DMA trigger is
enabled and will be asserted either upon completion of each
individual conversion performed as part of sequence B, or
upon completion of the entire B sequence of conversions,
depending on the MODE bit in the SEQB_CTRL
register.
1
SEQA_CTRL
ADC Conversion Sequence-A control Register: Controls triggering and channel selection for conversion sequence-A. Also specifies interrupt mode for sequence-A.
0x8
read-write
n
0x0
0x0
BURST
Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
27
28
CHANNELS
Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQA_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.
0
12
LOWPRIO
Set priority for sequence A.
29
30
ENUM
LOW_PRIORITY
Low priority. Any B trigger which occurs while an A
conversion sequence is active will be ignored and
lost.
0
HIGH_PRIORITY
High priority. Setting this bit to a 1 will permit
any enabled B sequence trigger (including a B sequence
software start) to immediately interrupt sequence A and
launch a B sequence in its place. The conversion currently
in progress will be terminated. The A sequence that was
interrupted will automatically resume after the B sequence
completes. The channel whose conversion was terminated will
be re-sampled and the conversion sequence will resume from
that point.
1
MODE
Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.
30
31
ENUM
END_OF_CONVERSION
End of conversion. The sequence A interrupt/DMA
trigger will be set at the end of each individual ADC
conversion performed under sequence A. This flag will mirror
the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit
in the SEQA_GDAT register will contribute to generation of
an overrun interrupt/DMA trigger if enabled.
0
END_OF_SEQUENCE
End of sequence. The sequence A interrupt/DMA
trigger will be set when the entire set of sequence-A
conversions completes. This flag will need to be explicitly
cleared by software or by the DMA-clear signal in this mode.
The OVERRUN bit in the SEQA_GDAT register will NOT
contribute to generation of an overrun interrupt/DMA trigger
since it is assumed this register may not be utilized in
this mode.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
26
SEQA_ENA
Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQA_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQA_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.
31
32
ENUM
DISABLED
Disabled. Sequence A is disabled. Sequence A
triggers are ignored. If this bit is cleared while sequence
A is in progress, the sequence will be halted at the end of
the current conversion. After the sequence is re-enabled, a
new trigger will be required to restart the sequence
beginning with the next enabled channel.
0
ENABLED
Enabled. Sequence A is enabled.
1
SINGLESTEP
When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.
28
29
START
Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero.
26
27
SYNCBYPASS
Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.
19
20
ENUM
ENABLE_TRIGGER_SYNCH
Enable trigger synchronization. The hardware
trigger bypass is not enabled.
0
BYPASS_TRIGGER_SYNCH
Bypass trigger synchronization. The hardware
trigger bypass is enabled.
1
TRIGGER
Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 351. In order to avoid generating a spurious trigger, it is recommended writing to this field only when the SEQA_ENA bit (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
12
18
TRIGPOL
Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when the SEQA_ENA bit (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
18
19
ENUM
NEGATIVE_EDGE
Negative edge. A negative edge launches the
conversion sequence on the selected trigger
input.
0
POSITIVE_EDGE
Positive edge. A positive edge launches the
conversion sequence on the selected trigger
input.
1
SEQA_GDAT
ADC Sequence-A Global Data Register. This register contains the result of the most recent ADC conversion performed under sequence-A
0x10
read-only
n
0x0
0x0
CHN
These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.).
26
30
DATAVALID
This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).
31
32
OVERRUN
This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled).
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.
4
16
THCMPCROSS
Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.
18
20
THCMPRANGE
Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).
16
18
SEQB_CTRL
ADC Conversion Sequence-B Control Register: Controls triggering and channel selection for conversion sequence-B. Also specifies interrupt mode for sequence-B.
0xC
read-write
n
0x0
0x0
BURST
Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence B triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated.
27
28
CHANNELS
Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while the SEQB_ENA bit (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write.
0
12
MODE
Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQB_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-B will be generated and which overrun conditions contribute to an overrun interrupt as described below.
30
31
ENUM
END_OF_CONVERSION
End of conversion. The sequence B interrupt/DMA
trigger will be set at the end of each individual ADC
conversion performed under sequence B. This flag will mirror
the DATAVALID bit in the SEQB_GDAT register. The OVERRUN bit
in the SEQB_GDAT register will contribute to generation of
an overrun interrupt/DMA trigger if enabled.
0
END_OF_SEQUENCE
End of sequence. The sequence B interrupt/DMA
trigger will be set when the entire set of sequence-B
conversions completes. This flag will need to be explicitly
cleared by software or by the DMA-clear signal in this mode.
The OVERRUN bit in the SEQB_GDAT register will NOT
contribute to generation of an overrun interrupt/DMA trigger
since it is assumed this register may not be utilized in
this mode.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
26
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
26
SEQB_ENA
Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQB_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQB_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.
31
32
ENUM
DISABLED
Disabled. Sequence B is disabled. Sequence B
triggers are ignored. If this bit is cleared while sequence
B is in progress, the sequence will be halted at the end of
the current conversion. After the sequence is re-enabled, a
new trigger will be required to restart the sequence
beginning with the next enabled channel.
0
ENABLED
Enabled. Sequence B is enabled.
1
SINGLESTEP
When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit.
28
29
START
Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero.
26
27
SYNCBYPASS
Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.
19
20
ENUM
ENABLE_SYNCHRONIZATI
Enable synchronization. The hardware trigger bypass
is not enabled.
0
BYPASS_SYNCHRONIZATI
Bypass synchronization. The hardware trigger bypass
is enabled.
1
TRIGGER
Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 351. In order to avoid generating a spurious trigger, it is recommended writing to this field only when the SEQB_ENA bit (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
12
18
TRIGPOL
Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when the SEQB_ENA bit (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
18
19
ENUM
NEGATIVE_EDGE
Negative edge. A negative edge launches the
conversion sequence on the selected trigger
input.
0
POSITIVE_EDGE
Positive edge. A positive edge launches the
conversion sequence on the selected trigger
input.
1
SEQB_GDAT
ADC Sequence-B Global Data Register. This register contains the result of the most recent ADC conversion performed under sequence-B
0x14
read-only
n
0x0
0x0
CHN
These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.).
26
30
DATAVALID
This bit is set to 1 at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQB_CTRL) for that sequence is set to 0 (and if the interrupt is enabled).
31
32
OVERRUN
This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQB_CTRL) for the corresponding sequence is set to 0 (and if the overrun interrupt is enabled).
30
31
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
RESULT
This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read.
4
16
THCMPCROSS
Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred.
18
20
THCMPRANGE
Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH).
16
18
STARTUP
ADC Startup Register (typically only used by the ADC API).
0x6C
read-write
n
0x0
0x0
ADC_ENA
ADC Enable bit. This bit can only be set to a 1 by software. It is cleared automatically whenever the ADC is powered down. This bit must not be set until at least 10 microseconds after the ADC is powered up (typically by altering a system-level ADC power control bit).
0
1
ADC_INT
tbd
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
32
THR0_HIGH
ADC High Compare Threshold Register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
0x58
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
THRHIGH
High threshold value against which ADC results will be compared
4
16
THR0_LOW
ADC Low Compare Threshold Register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0.
0x50
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
THRLOW
Low threshold value against which ADC results will be compared
4
16
THR1_HIGH
ADC High Compare Threshold Register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
0x5C
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
THRHIGH
High threshold value against which ADC results will be compared
4
16
THR1_LOW
ADC Low Compare Threshold Register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
0x54
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
THRLOW
Low threshold value against which ADC results will be compared
4
16
ADVSYSCON
Advanced System configuration
ADVSYSCON
0x0
0x0
0x1000
registers
n
BOD
1
BODCTRL
Brown-Out Detect control
0x44
read-write
n
0x0
0x0
BODINTVAL
BOD interrupt level
2
4
ENUM
LEVEL_0_2
Level 0: 2.05 V
0x0
LEVEL_1_2
Level 1: 2.45 V
0x1
LEVEL_2_2
Level 2: 2.75 V
0x2
LEVEL_3_3
Level 3: 3.05 V
0x3
BODRSTENA
BOD reset enable
4
5
ENUM
DISABLE_RESET_FUNCTI
Disable reset function.
0
ENABLE_RESET_FUNCTIO
Enable reset function.
1
BODRSTLEV
BOD reset level
0
2
ENUM
LEVEL_0_1
Level 0: 1.5 V
0x0
LEVEL_1_1
Level 1: 1.85 V
0x1
LEVEL_2_2
Level 2: 2.0 V
0x2
LEVEL_3_2
Level 3: 2.3 V
0x3
RESERVED
Reserved
5
32
ASYNCSYSCON
Asynchronous system configuration
ASYNCSYSCON
0x0
0x0
0x1000
registers
n
ASYNCAPBCLKCTRL
Async peripheral clock control
0x10
read-write
n
0x0
0x0
FRG0
Controls the clock for the Fractional Rate Generator used with the USARTs. 0 = Disable; 1 = Enable.
15
16
I2C0
Controls the clock for I2C0. 0 = Disable; 1 = Enable.
5
6
I2C1
Controls the clock for I2C1. 0 = Disable; 1 = Enable.
6
7
I2C2
Controls the clock for I2C2. 0 = Disable; 1 = Enable.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
11
13
RESERVED
Reserved. Read value is undefined, only zero should be written.
11
13
SPI0
Controls the clock for SPI0. 0 = Disable; 1 = Enable.
9
10
SPI1
Controls the clock for SPI1. 0 = Disable; 1 = Enable.
10
11
TIMER0
Controls the clock for TIMER0. 0 = Disable; 1 = Enable.
13
14
TIMER1
Controls the clock for TIMER1. 0 = Disable; 1 = Enable.
14
15
USART0
Controls the clock for USART0. 0 = Disable; 1 = Enable.
1
2
USART1
Controls the clock for USART1. 0 = Disable; 1 = Enable.
2
3
USART2
Controls the clock for USART2. 0 = Disable; 1 = Enable.
3
4
USART3
Controls the clock for USART3. 0 = Disable; 1 = Enable.
4
5
ASYNCAPBCLKCTRLCLR
Clear bits in ASYNCAPBCLKCTRL
0x18
write-only
n
0x0
0x0
ACLK_CLR
Writing ones to this register clears the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
0
32
ASYNCAPBCLKCTRLSET
Set bits in ASYNCAPBCLKCTRL
0x14
write-only
n
0x0
0x0
ACLK_SET
Writing ones to this register sets the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in AYSNCPRESETCTRL are reserved and only zeroes should be written to them.
0
32
ASYNCAPBCLKSELA
Async APB clock source select A
0x20
read-write
n
0x0
0x0
RESERVED
Reserved
2
32
SEL
Clock source for asynchronous clock source selector A
0
2
ENUM
IRC_OSCILLATOR
IRC Oscillator
0x0
WATCHDOG_OSCILLATOR
Watchdog oscillator
0x1
RESERVED
Reserved
0x2
RESERVED
Reserved
0x2
ASYNCAPBCLKSELB
Async APB clock source select B
0x24
read-write
n
0x0
0x0
RESERVED
Reserved
2
32
SEL
Clock source for asynchronous clock source selector B.
0
2
ENUM
MAIN_CLOCK
Main clock
0x0
CLKIN
CLKIN
0x1
SYSTEM_PLL_OUTPUT
System PLL output.
0x2
ASYNCAPBCLKSELA
ASYNCAPBCLKSELA. Clock selected by the
ASYNCAPBCLKSELA register.
0x3
ASYNCCLKDIV
Async APB clock divider
0x28
read-write
n
0x0
0x0
DIV
Asynchronous APB clock divider value. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255.
0
8
RESERVED
Reserved
8
32
AYSNCPRESETCTRL
Async peripheral reset control
0x0
read-write
n
0x0
0x0
FRG0
FRG reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
15
16
I2C0
I2C0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
5
6
I2C1
I2C1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
6
7
I2C2
I2C2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
7
8
RESERVED
Reserved
0
1
RESERVED
Reserved
8
9
RESERVED
Reserved
11
13
RESERVED
Reserved
11
13
SPI0
SPI0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
9
10
SPI1
SPI1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
10
11
TIMER0
Timer 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
13
14
TIMER1
Timer 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
14
15
USART0
USART0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1
2
USART1
USART1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
2
3
USART2
USART2 reset control.0 = Clear reset to this function. 1 = Assert reset to this function.
3
4
USART3
USART3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
4
5
AYSNCPRESETCTRLCLR
Clear bits in AYSNCPRESETCTRL
0x8
write-only
n
0x0
0x0
ARST_CLR
Writing ones to this register clears the corresponding bit or bits in the AYSNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in AYSNCPRESETCTRL are reserved and only zeroes should be written to them.
0
32
AYSNCPRESETCTRLSET
Set bits in AYSNCPRESETCTRL
0x4
write-only
n
0x0
0x0
ARST_SET
Writing ones to this register sets the corresponding bit or bits in the AYSNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in AYSNCPRESETCTRL are reserved and only zeroes should be written to them.
0
32
BODCTRL
Brown-Out Detect control
0x44
read-write
n
0x0
0x0
BODINTVAL
BOD interrupt level
2
4
ENUM
LEVEL_0_2
Level 0: 2.05 V
0x0
LEVEL_1_2
Level 1: 2.45 V
0x1
LEVEL_2_2
Level 2: 2.75 V
0x2
LEVEL_3_3
Level 3: 3.05 V
0x3
BODRSTENA
BOD reset enable
4
5
ENUM
DISABLE_RESET_FUNCTI
Disable reset function.
0
ENABLE_RESET_FUNCTIO
Enable reset function.
1
BODRSTLEV
BOD reset level
0
2
ENUM
LEVEL_0_1
Level 0: 1.5 V
0x0
LEVEL_1_1
Level 1: 1.85 V
0x1
LEVEL_2_2
Level 2: 2.0 V
0x2
LEVEL_3_2
Level 3: 2.3 V
0x3
RESERVED
Reserved
5
32
FRGCTRL
USART fractional rate generator control
0x30
read-write
n
0x0
0x0
DIV
Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.
0
8
MULT
Numerator of the fractional divider. MULT is equal to the programmed value.
8
16
RESERVED
Reserved
16
32
CRC
CRC engine
CRC
0x0
0x0
0x1000
registers
n
MODE
CRC mode register
0x0
read-write
n
0x0
0x0
BIT_RVS_SUM
CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM
4
5
BIT_RVS_WR
Data bit order: 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte)
2
3
CMPL_SUM
CRC sum complement: 1= 1s complement for CRC_SUM 0=No 1s complement for CRC_SUM
5
6
CMPL_WR
Data complement: 1= 1s complement for CRC_WR_DATA 0= No 1s complement for CRC_WR_DATA
3
4
CRC_POLY
CRC polynom: 1X= CRC-32 polynomial 01= CRC-16 polynomial 00= CRC-CCITT polynomial
0
2
Reserved
Always 0 when read
6
32
SEED
CRC seed register
0x4
read-write
n
0x0
0x0
CRC_SEED
A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1s complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.
0
32
SUM
CRC checksum register
0x8
read-only
n
0x0
0x0
CRC_SUM
The most recent CRC sum can be read through this register with selected bit order and 1s complement post-processes.
0
32
WR_DATA
CRC data register
0x8
write-only
n
0x0
0x0
CRC_WR_DATA
Data written to this register will be taken to perform CRC calculation with selected bit order and 1s complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.
0
32
CT32B0
Standard counter/timer 0
CT32B2
0x0
0x0
0x1000
registers
n
CT32B0
11
CCR
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x28
read-write
n
0x0
0x0
CAP0FE
Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
1
2
CAP0I
Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2
3
CAP0RE
Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
0
1
CAP1FE
Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
4
5
CAP1I
Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5
6
CAP1RE
Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
3
4
CAP2FE
Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
7
8
CAP2I
Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
8
9
CAP2RE
Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
6
7
CAP3FE
Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
10
11
CAP3I
Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
11
12
CAP3RE
Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
CR0
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x58
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR1
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x88
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR2
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xBC
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR3
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xF4
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CTCR
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x70
read-write
n
0x0
0x0
CINSEL
Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
2
4
ENUM
CHANNEL_0
Channel 0. CAPn.0 for TIMERn
0x0
CHANNEL_1
Channel 1. CAPn.1 for TIMERn
0x1
CHANNEL_2
Channel 2. CAPn.2 for TIMERn
0x2
CHANNEL_3
Channel 3. CAPn.3 for TIMERn
0x3
CTMODE
Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
0
2
ENUM
TIMER_MODE
Timer Mode. Incremented every rising PCLK
edge.
0x0
COUNTER_MODE_RISING
Counter Mode rising edge. TC is incremented on
rising edges on the CAP input selected by bits
3:2.
0x1
COUNTER_MODE_FALLING
Counter Mode falling edge. TC is incremented on
falling edges on the CAP input selected by bits
3:2.
0x2
COUNTER_MODE_DUAL_ED
Counter Mode dual edge. TC is incremented on both
edges on the CAP input selected by bits 3:2.
0x3
ENCC
Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SELCC
Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
5
8
ENUM
CHANNEL_0_RISING_EDG
Channel 0 Rising Edge. Rising edge of the signal on
capture channel 0 clears the timer (if bit 4 is
set).
0x0
CHANNEL_0_FALLING_ED
Channel 0 Falling Edge. Falling edge of the signal
on capture channel 0 clears the timer (if bit 4 is
set).
0x1
CHANNEL_1_RISING_EDG
Channel 1 Rising Edge. Rising edge of the signal on
capture channel 1 clears the timer (if bit 4 is
set).
0x2
CHANNEL_1_FALLING_ED
Channel 1 Falling Edge. Falling edge of the signal
on capture channel 1 clears the timer (if bit 4 is
set).
0x3
CHANNEL_2_RISING_EDG
Channel 2 Rising Edge. Rising edge of the signal on
capture channel 2 clears the timer (if bit 4 is
set).
0x4
CHANNEL_2_FALLING_ED
Channel 2 Falling Edge. Falling edge of the signal
on capture channel 2 clears the timer (if bit 4 is
set).
0x5
EMR
External Match Register. The EMR controls the match function and the external match pins.
0x3C
read-write
n
0x0
0x0
EM0
External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
0
1
EM1
External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1
2
EM2
External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2
3
EM3
External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3
4
EMC0
External Match Control 0. Determines the functionality of External Match 0.
4
6
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT0 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT0 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC1
External Match Control 1. Determines the functionality of External Match 1.
6
8
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT1 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT1 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC2
External Match Control 2. Determines the functionality of External Match 2.
8
10
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT2 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT2 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC3
External Match Control 3. Determines the functionality of External Match 3.
10
12
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT3 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT3 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
IR
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
0x0
read-write
n
0x0
0x0
CR0INT
Interrupt flag for capture channel 0 event.
4
5
CR1INT
Interrupt flag for capture channel 1 event.
5
6
CR2INT
Interrupt flag for capture channel 2 event.
6
7
CR3INT
Interrupt flag for capture channel 3 event.
7
8
MR0INT
Interrupt flag for match channel 0.
0
1
MR1INT
Interrupt flag for match channel 1.
1
2
MR2INT
Interrupt flag for match channel 2.
2
3
MR3INT
Interrupt flag for match channel 3.
3
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
MCR
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x14
read-write
n
0x0
0x0
MR0I
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
0
1
MR0R
Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1
2
MR0S
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
2
3
MR1I
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.
3
4
MR1R
Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
4
5
MR1S
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
5
6
MR2I
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
6
7
MR2R
Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
7
8
MR2S
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
8
9
MR3I
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
9
10
MR3R
Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
10
11
MR3S
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
11
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
MR0
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x30
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR1
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR2
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x6C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR3
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x90
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
PC
Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x10
read-write
n
0x0
0x0
PCVAL
Prescale counter value.
0
32
PR
Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
0xC
read-write
n
0x0
0x0
PRVAL
Prescale counter value.
0
32
PWMC
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
0x74
read-write
n
0x0
0x0
PWMEN0
PWM mode enable for channel0.
0
1
ENUM
MATCH
Match. CT32Bn_MAT0 is controlled by
EM0.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT0.
1
PWMEN1
PWM mode enable for channel1.
1
2
ENUM
MATCH
Match. CT32Bn_MAT01 is controlled by
EM1.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT1.
1
PWMEN2
PWM mode enable for channel2.
2
3
ENUM
MATCH
Match. CT32Bn_MAT2 is controlled by
EM2.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT2.
1
PWMEN3
PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3
4
ENUM
MATCH
Match. CT32Bn_MAT3 is controlled by
EM3.
0
PWM
PWM. PWM mode is enabled for
CT132Bn_MAT3.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
TC
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x8
read-write
n
0x0
0x0
TCVAL
Timer counter value.
0
32
TCR
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x4
read-write
n
0x0
0x0
CEN
Counter enable.
0
1
ENUM
DISABLED
Disabled.The counters are disabled.
0
ENABLED
Enabled. The Timer Counter and Prescale Counter are
enabled.
1
CRST
Counter reset.
1
2
ENUM
DISABLED
Disabled. Do nothing.
0
ENABLED
Enabled. The Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until TCR[1] is returned to
zero.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
32
CT32B1
Standard counter/timer 1
CT32B2
0x0
0x0
0x1000
registers
n
CT32B1
12
CCR
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x28
read-write
n
0x0
0x0
CAP0FE
Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
1
2
CAP0I
Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2
3
CAP0RE
Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
0
1
CAP1FE
Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
4
5
CAP1I
Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5
6
CAP1RE
Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
3
4
CAP2FE
Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
7
8
CAP2I
Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
8
9
CAP2RE
Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
6
7
CAP3FE
Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
10
11
CAP3I
Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
11
12
CAP3RE
Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
CR0
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x58
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR1
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x88
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR2
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xBC
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR3
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xF4
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CTCR
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x70
read-write
n
0x0
0x0
CINSEL
Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
2
4
ENUM
CHANNEL_0
Channel 0. CAPn.0 for TIMERn
0x0
CHANNEL_1
Channel 1. CAPn.1 for TIMERn
0x1
CHANNEL_2
Channel 2. CAPn.2 for TIMERn
0x2
CHANNEL_3
Channel 3. CAPn.3 for TIMERn
0x3
CTMODE
Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
0
2
ENUM
TIMER_MODE
Timer Mode. Incremented every rising PCLK
edge.
0x0
COUNTER_MODE_RISING
Counter Mode rising edge. TC is incremented on
rising edges on the CAP input selected by bits
3:2.
0x1
COUNTER_MODE_FALLING
Counter Mode falling edge. TC is incremented on
falling edges on the CAP input selected by bits
3:2.
0x2
COUNTER_MODE_DUAL_ED
Counter Mode dual edge. TC is incremented on both
edges on the CAP input selected by bits 3:2.
0x3
ENCC
Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SELCC
Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
5
8
ENUM
CHANNEL_0_RISING_EDG
Channel 0 Rising Edge. Rising edge of the signal on
capture channel 0 clears the timer (if bit 4 is
set).
0x0
CHANNEL_0_FALLING_ED
Channel 0 Falling Edge. Falling edge of the signal
on capture channel 0 clears the timer (if bit 4 is
set).
0x1
CHANNEL_1_RISING_EDG
Channel 1 Rising Edge. Rising edge of the signal on
capture channel 1 clears the timer (if bit 4 is
set).
0x2
CHANNEL_1_FALLING_ED
Channel 1 Falling Edge. Falling edge of the signal
on capture channel 1 clears the timer (if bit 4 is
set).
0x3
CHANNEL_2_RISING_EDG
Channel 2 Rising Edge. Rising edge of the signal on
capture channel 2 clears the timer (if bit 4 is
set).
0x4
CHANNEL_2_FALLING_ED
Channel 2 Falling Edge. Falling edge of the signal
on capture channel 2 clears the timer (if bit 4 is
set).
0x5
EMR
External Match Register. The EMR controls the match function and the external match pins.
0x3C
read-write
n
0x0
0x0
EM0
External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
0
1
EM1
External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1
2
EM2
External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2
3
EM3
External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3
4
EMC0
External Match Control 0. Determines the functionality of External Match 0.
4
6
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT0 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT0 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC1
External Match Control 1. Determines the functionality of External Match 1.
6
8
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT1 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT1 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC2
External Match Control 2. Determines the functionality of External Match 2.
8
10
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT2 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT2 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC3
External Match Control 3. Determines the functionality of External Match 3.
10
12
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT3 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT3 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
IR
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
0x0
read-write
n
0x0
0x0
CR0INT
Interrupt flag for capture channel 0 event.
4
5
CR1INT
Interrupt flag for capture channel 1 event.
5
6
CR2INT
Interrupt flag for capture channel 2 event.
6
7
CR3INT
Interrupt flag for capture channel 3 event.
7
8
MR0INT
Interrupt flag for match channel 0.
0
1
MR1INT
Interrupt flag for match channel 1.
1
2
MR2INT
Interrupt flag for match channel 2.
2
3
MR3INT
Interrupt flag for match channel 3.
3
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
MCR
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x14
read-write
n
0x0
0x0
MR0I
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
0
1
MR0R
Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1
2
MR0S
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
2
3
MR1I
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.
3
4
MR1R
Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
4
5
MR1S
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
5
6
MR2I
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
6
7
MR2R
Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
7
8
MR2S
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
8
9
MR3I
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
9
10
MR3R
Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
10
11
MR3S
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
11
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
MR0
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x30
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR1
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR2
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x6C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR3
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x90
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
PC
Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x10
read-write
n
0x0
0x0
PCVAL
Prescale counter value.
0
32
PR
Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
0xC
read-write
n
0x0
0x0
PRVAL
Prescale counter value.
0
32
PWMC
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
0x74
read-write
n
0x0
0x0
PWMEN0
PWM mode enable for channel0.
0
1
ENUM
MATCH
Match. CT32Bn_MAT0 is controlled by
EM0.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT0.
1
PWMEN1
PWM mode enable for channel1.
1
2
ENUM
MATCH
Match. CT32Bn_MAT01 is controlled by
EM1.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT1.
1
PWMEN2
PWM mode enable for channel2.
2
3
ENUM
MATCH
Match. CT32Bn_MAT2 is controlled by
EM2.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT2.
1
PWMEN3
PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3
4
ENUM
MATCH
Match. CT32Bn_MAT3 is controlled by
EM3.
0
PWM
PWM. PWM mode is enabled for
CT132Bn_MAT3.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
TC
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x8
read-write
n
0x0
0x0
TCVAL
Timer counter value.
0
32
TCR
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x4
read-write
n
0x0
0x0
CEN
Counter enable.
0
1
ENUM
DISABLED
Disabled.The counters are disabled.
0
ENABLED
Enabled. The Timer Counter and Prescale Counter are
enabled.
1
CRST
Counter reset.
1
2
ENUM
DISABLED
Disabled. Do nothing.
0
ENABLED
Enabled. The Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until TCR[1] is returned to
zero.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
32
CT32B2
Standard counter/timer 2
CT32B2
0x0
0x0
0x1000
registers
n
CT32B2
13
CCR
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x28
read-write
n
0x0
0x0
CAP0FE
Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
1
2
CAP0I
Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2
3
CAP0RE
Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
0
1
CAP1FE
Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
4
5
CAP1I
Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5
6
CAP1RE
Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
3
4
CAP2FE
Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
7
8
CAP2I
Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
8
9
CAP2RE
Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
6
7
CAP3FE
Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
10
11
CAP3I
Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
11
12
CAP3RE
Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
CR0
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x58
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR1
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x88
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR2
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xBC
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR3
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xF4
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CTCR
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x70
read-write
n
0x0
0x0
CINSEL
Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
2
4
ENUM
CHANNEL_0
Channel 0. CAPn.0 for TIMERn
0x0
CHANNEL_1
Channel 1. CAPn.1 for TIMERn
0x1
CHANNEL_2
Channel 2. CAPn.2 for TIMERn
0x2
CHANNEL_3
Channel 3. CAPn.3 for TIMERn
0x3
CTMODE
Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
0
2
ENUM
TIMER_MODE
Timer Mode. Incremented every rising PCLK
edge.
0x0
COUNTER_MODE_RISING
Counter Mode rising edge. TC is incremented on
rising edges on the CAP input selected by bits
3:2.
0x1
COUNTER_MODE_FALLING
Counter Mode falling edge. TC is incremented on
falling edges on the CAP input selected by bits
3:2.
0x2
COUNTER_MODE_DUAL_ED
Counter Mode dual edge. TC is incremented on both
edges on the CAP input selected by bits 3:2.
0x3
ENCC
Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SELCC
Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
5
8
ENUM
CHANNEL_0_RISING_EDG
Channel 0 Rising Edge. Rising edge of the signal on
capture channel 0 clears the timer (if bit 4 is
set).
0x0
CHANNEL_0_FALLING_ED
Channel 0 Falling Edge. Falling edge of the signal
on capture channel 0 clears the timer (if bit 4 is
set).
0x1
CHANNEL_1_RISING_EDG
Channel 1 Rising Edge. Rising edge of the signal on
capture channel 1 clears the timer (if bit 4 is
set).
0x2
CHANNEL_1_FALLING_ED
Channel 1 Falling Edge. Falling edge of the signal
on capture channel 1 clears the timer (if bit 4 is
set).
0x3
CHANNEL_2_RISING_EDG
Channel 2 Rising Edge. Rising edge of the signal on
capture channel 2 clears the timer (if bit 4 is
set).
0x4
CHANNEL_2_FALLING_ED
Channel 2 Falling Edge. Falling edge of the signal
on capture channel 2 clears the timer (if bit 4 is
set).
0x5
EMR
External Match Register. The EMR controls the match function and the external match pins.
0x3C
read-write
n
0x0
0x0
EM0
External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
0
1
EM1
External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1
2
EM2
External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2
3
EM3
External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3
4
EMC0
External Match Control 0. Determines the functionality of External Match 0.
4
6
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT0 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT0 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC1
External Match Control 1. Determines the functionality of External Match 1.
6
8
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT1 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT1 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC2
External Match Control 2. Determines the functionality of External Match 2.
8
10
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT2 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT2 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC3
External Match Control 3. Determines the functionality of External Match 3.
10
12
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT3 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT3 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
IR
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
0x0
read-write
n
0x0
0x0
CR0INT
Interrupt flag for capture channel 0 event.
4
5
CR1INT
Interrupt flag for capture channel 1 event.
5
6
CR2INT
Interrupt flag for capture channel 2 event.
6
7
CR3INT
Interrupt flag for capture channel 3 event.
7
8
MR0INT
Interrupt flag for match channel 0.
0
1
MR1INT
Interrupt flag for match channel 1.
1
2
MR2INT
Interrupt flag for match channel 2.
2
3
MR3INT
Interrupt flag for match channel 3.
3
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
MCR
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x14
read-write
n
0x0
0x0
MR0I
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
0
1
MR0R
Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1
2
MR0S
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
2
3
MR1I
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.
3
4
MR1R
Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
4
5
MR1S
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
5
6
MR2I
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
6
7
MR2R
Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
7
8
MR2S
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
8
9
MR3I
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
9
10
MR3R
Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
10
11
MR3S
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
11
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
MR0
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x30
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR1
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR2
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x6C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR3
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x90
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
PC
Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x10
read-write
n
0x0
0x0
PCVAL
Prescale counter value.
0
32
PR
Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
0xC
read-write
n
0x0
0x0
PRVAL
Prescale counter value.
0
32
PWMC
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
0x74
read-write
n
0x0
0x0
PWMEN0
PWM mode enable for channel0.
0
1
ENUM
MATCH
Match. CT32Bn_MAT0 is controlled by
EM0.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT0.
1
PWMEN1
PWM mode enable for channel1.
1
2
ENUM
MATCH
Match. CT32Bn_MAT01 is controlled by
EM1.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT1.
1
PWMEN2
PWM mode enable for channel2.
2
3
ENUM
MATCH
Match. CT32Bn_MAT2 is controlled by
EM2.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT2.
1
PWMEN3
PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3
4
ENUM
MATCH
Match. CT32Bn_MAT3 is controlled by
EM3.
0
PWM
PWM. PWM mode is enabled for
CT132Bn_MAT3.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
TC
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x8
read-write
n
0x0
0x0
TCVAL
Timer counter value.
0
32
TCR
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x4
read-write
n
0x0
0x0
CEN
Counter enable.
0
1
ENUM
DISABLED
Disabled.The counters are disabled.
0
ENABLED
Enabled. The Timer Counter and Prescale Counter are
enabled.
1
CRST
Counter reset.
1
2
ENUM
DISABLED
Disabled. Do nothing.
0
ENABLED
Enabled. The Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until TCR[1] is returned to
zero.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
32
CT32B3
Standard counter/timer 3
CT32B2
0x0
0x0
0x1000
registers
n
CT32B3
14
CCR
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x28
read-write
n
0x0
0x0
CAP0FE
Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
1
2
CAP0I
Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2
3
CAP0RE
Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
0
1
CAP1FE
Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
4
5
CAP1I
Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5
6
CAP1RE
Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
3
4
CAP2FE
Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
7
8
CAP2I
Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
8
9
CAP2RE
Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
6
7
CAP3FE
Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
10
11
CAP3I
Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
11
12
CAP3RE
Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
CR0
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x58
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR1
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x88
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR2
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xBC
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR3
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xF4
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CTCR
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x70
read-write
n
0x0
0x0
CINSEL
Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
2
4
ENUM
CHANNEL_0
Channel 0. CAPn.0 for TIMERn
0x0
CHANNEL_1
Channel 1. CAPn.1 for TIMERn
0x1
CHANNEL_2
Channel 2. CAPn.2 for TIMERn
0x2
CHANNEL_3
Channel 3. CAPn.3 for TIMERn
0x3
CTMODE
Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
0
2
ENUM
TIMER_MODE
Timer Mode. Incremented every rising PCLK
edge.
0x0
COUNTER_MODE_RISING
Counter Mode rising edge. TC is incremented on
rising edges on the CAP input selected by bits
3:2.
0x1
COUNTER_MODE_FALLING
Counter Mode falling edge. TC is incremented on
falling edges on the CAP input selected by bits
3:2.
0x2
COUNTER_MODE_DUAL_ED
Counter Mode dual edge. TC is incremented on both
edges on the CAP input selected by bits 3:2.
0x3
ENCC
Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SELCC
Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
5
8
ENUM
CHANNEL_0_RISING_EDG
Channel 0 Rising Edge. Rising edge of the signal on
capture channel 0 clears the timer (if bit 4 is
set).
0x0
CHANNEL_0_FALLING_ED
Channel 0 Falling Edge. Falling edge of the signal
on capture channel 0 clears the timer (if bit 4 is
set).
0x1
CHANNEL_1_RISING_EDG
Channel 1 Rising Edge. Rising edge of the signal on
capture channel 1 clears the timer (if bit 4 is
set).
0x2
CHANNEL_1_FALLING_ED
Channel 1 Falling Edge. Falling edge of the signal
on capture channel 1 clears the timer (if bit 4 is
set).
0x3
CHANNEL_2_RISING_EDG
Channel 2 Rising Edge. Rising edge of the signal on
capture channel 2 clears the timer (if bit 4 is
set).
0x4
CHANNEL_2_FALLING_ED
Channel 2 Falling Edge. Falling edge of the signal
on capture channel 2 clears the timer (if bit 4 is
set).
0x5
EMR
External Match Register. The EMR controls the match function and the external match pins.
0x3C
read-write
n
0x0
0x0
EM0
External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
0
1
EM1
External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1
2
EM2
External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2
3
EM3
External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3
4
EMC0
External Match Control 0. Determines the functionality of External Match 0.
4
6
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT0 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT0 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC1
External Match Control 1. Determines the functionality of External Match 1.
6
8
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT1 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT1 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC2
External Match Control 2. Determines the functionality of External Match 2.
8
10
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT2 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT2 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC3
External Match Control 3. Determines the functionality of External Match 3.
10
12
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT3 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT3 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
IR
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
0x0
read-write
n
0x0
0x0
CR0INT
Interrupt flag for capture channel 0 event.
4
5
CR1INT
Interrupt flag for capture channel 1 event.
5
6
CR2INT
Interrupt flag for capture channel 2 event.
6
7
CR3INT
Interrupt flag for capture channel 3 event.
7
8
MR0INT
Interrupt flag for match channel 0.
0
1
MR1INT
Interrupt flag for match channel 1.
1
2
MR2INT
Interrupt flag for match channel 2.
2
3
MR3INT
Interrupt flag for match channel 3.
3
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
MCR
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x14
read-write
n
0x0
0x0
MR0I
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
0
1
MR0R
Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1
2
MR0S
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
2
3
MR1I
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.
3
4
MR1R
Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
4
5
MR1S
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
5
6
MR2I
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
6
7
MR2R
Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
7
8
MR2S
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
8
9
MR3I
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
9
10
MR3R
Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
10
11
MR3S
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
11
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
MR0
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x30
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR1
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR2
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x6C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR3
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x90
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
PC
Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x10
read-write
n
0x0
0x0
PCVAL
Prescale counter value.
0
32
PR
Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
0xC
read-write
n
0x0
0x0
PRVAL
Prescale counter value.
0
32
PWMC
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
0x74
read-write
n
0x0
0x0
PWMEN0
PWM mode enable for channel0.
0
1
ENUM
MATCH
Match. CT32Bn_MAT0 is controlled by
EM0.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT0.
1
PWMEN1
PWM mode enable for channel1.
1
2
ENUM
MATCH
Match. CT32Bn_MAT01 is controlled by
EM1.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT1.
1
PWMEN2
PWM mode enable for channel2.
2
3
ENUM
MATCH
Match. CT32Bn_MAT2 is controlled by
EM2.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT2.
1
PWMEN3
PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3
4
ENUM
MATCH
Match. CT32Bn_MAT3 is controlled by
EM3.
0
PWM
PWM. PWM mode is enabled for
CT132Bn_MAT3.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
TC
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x8
read-write
n
0x0
0x0
TCVAL
Timer counter value.
0
32
TCR
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x4
read-write
n
0x0
0x0
CEN
Counter enable.
0
1
ENUM
DISABLED
Disabled.The counters are disabled.
0
ENABLED
Enabled. The Timer Counter and Prescale Counter are
enabled.
1
CRST
Counter reset.
1
2
ENUM
DISABLED
Disabled. Do nothing.
0
ENABLED
Enabled. The Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until TCR[1] is returned to
zero.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
32
CT32B4
Standard counter/timer 4
CT32B2
0x0
0x0
0x1000
registers
n
CT32B4
15
CCR
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
0x28
read-write
n
0x0
0x0
CAP0FE
Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
1
2
CAP0I
Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
2
3
CAP0RE
Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
0
1
CAP1FE
Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
4
5
CAP1I
Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
5
6
CAP1RE
Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
3
4
CAP2FE
Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
7
8
CAP2I
Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
8
9
CAP2RE
Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
6
7
CAP3FE
Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
10
11
CAP3I
Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
11
12
CAP3RE
Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
CR0
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x58
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR1
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0x88
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR2
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xBC
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CR3
Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.
0xF4
read-only
n
0x0
0x0
CAP
Timer counter capture value.
0
32
CTCR
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
0x70
read-write
n
0x0
0x0
CINSEL
Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
2
4
ENUM
CHANNEL_0
Channel 0. CAPn.0 for TIMERn
0x0
CHANNEL_1
Channel 1. CAPn.1 for TIMERn
0x1
CHANNEL_2
Channel 2. CAPn.2 for TIMERn
0x2
CHANNEL_3
Channel 3. CAPn.3 for TIMERn
0x3
CTMODE
Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
0
2
ENUM
TIMER_MODE
Timer Mode. Incremented every rising PCLK
edge.
0x0
COUNTER_MODE_RISING
Counter Mode rising edge. TC is incremented on
rising edges on the CAP input selected by bits
3:2.
0x1
COUNTER_MODE_FALLING
Counter Mode falling edge. TC is incremented on
falling edges on the CAP input selected by bits
3:2.
0x2
COUNTER_MODE_DUAL_ED
Counter Mode dual edge. TC is incremented on both
edges on the CAP input selected by bits 3:2.
0x3
ENCC
Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SELCC
Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
5
8
ENUM
CHANNEL_0_RISING_EDG
Channel 0 Rising Edge. Rising edge of the signal on
capture channel 0 clears the timer (if bit 4 is
set).
0x0
CHANNEL_0_FALLING_ED
Channel 0 Falling Edge. Falling edge of the signal
on capture channel 0 clears the timer (if bit 4 is
set).
0x1
CHANNEL_1_RISING_EDG
Channel 1 Rising Edge. Rising edge of the signal on
capture channel 1 clears the timer (if bit 4 is
set).
0x2
CHANNEL_1_FALLING_ED
Channel 1 Falling Edge. Falling edge of the signal
on capture channel 1 clears the timer (if bit 4 is
set).
0x3
CHANNEL_2_RISING_EDG
Channel 2 Rising Edge. Rising edge of the signal on
capture channel 2 clears the timer (if bit 4 is
set).
0x4
CHANNEL_2_FALLING_ED
Channel 2 Falling Edge. Falling edge of the signal
on capture channel 2 clears the timer (if bit 4 is
set).
0x5
EMR
External Match Register. The EMR controls the match function and the external match pins.
0x3C
read-write
n
0x0
0x0
EM0
External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
0
1
EM1
External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
1
2
EM2
External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
2
3
EM3
External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
3
4
EMC0
External Match Control 0. Determines the functionality of External Match 0.
4
6
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT0 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT0 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC1
External Match Control 1. Determines the functionality of External Match 1.
6
8
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT1 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT1 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC2
External Match Control 2. Determines the functionality of External Match 2.
8
10
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT2 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT2 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
EMC3
External Match Control 3. Determines the functionality of External Match 3.
10
12
ENUM
DO_NOTHING
Do Nothing.
0x0
CLEAR
Clear. Clear the corresponding External Match
bit/output to 0 (MAT3 pin is LOW if pinned
out).
0x1
SET
Set. Set the corresponding External Match
bit/output to 1 (MAT3 pin is HIGH if pinned
out).
0x2
TOGGLE
Toggle. Toggle the corresponding External Match
bit/output.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
IR
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
0x0
read-write
n
0x0
0x0
CR0INT
Interrupt flag for capture channel 0 event.
4
5
CR1INT
Interrupt flag for capture channel 1 event.
5
6
CR2INT
Interrupt flag for capture channel 2 event.
6
7
CR3INT
Interrupt flag for capture channel 3 event.
7
8
MR0INT
Interrupt flag for match channel 0.
0
1
MR1INT
Interrupt flag for match channel 1.
1
2
MR2INT
Interrupt flag for match channel 2.
2
3
MR3INT
Interrupt flag for match channel 3.
3
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
MCR
Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
0x14
read-write
n
0x0
0x0
MR0I
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.
0
1
MR0R
Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.
1
2
MR0S
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.
2
3
MR1I
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.
3
4
MR1R
Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.
4
5
MR1S
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.
5
6
MR2I
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.
6
7
MR2R
Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.
7
8
MR2S
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.
8
9
MR3I
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.
9
10
MR3R
Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.
10
11
MR3S
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.
11
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
32
MR0
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x30
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR1
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x4C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR2
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x6C
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
MR3
Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
0x90
read-write
n
0x0
0x0
MATCH
Timer counter match value.
0
32
PC
Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
0x10
read-write
n
0x0
0x0
PCVAL
Prescale counter value.
0
32
PR
Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
0xC
read-write
n
0x0
0x0
PRVAL
Prescale counter value.
0
32
PWMC
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
0x74
read-write
n
0x0
0x0
PWMEN0
PWM mode enable for channel0.
0
1
ENUM
MATCH
Match. CT32Bn_MAT0 is controlled by
EM0.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT0.
1
PWMEN1
PWM mode enable for channel1.
1
2
ENUM
MATCH
Match. CT32Bn_MAT01 is controlled by
EM1.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT1.
1
PWMEN2
PWM mode enable for channel2.
2
3
ENUM
MATCH
Match. CT32Bn_MAT2 is controlled by
EM2.
0
PWM
PWM. PWM mode is enabled for
CT32Bn_MAT2.
1
PWMEN3
PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
3
4
ENUM
MATCH
Match. CT32Bn_MAT3 is controlled by
EM3.
0
PWM
PWM. PWM mode is enabled for
CT132Bn_MAT3.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
TC
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
0x8
read-write
n
0x0
0x0
TCVAL
Timer counter value.
0
32
TCR
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
0x4
read-write
n
0x0
0x0
CEN
Counter enable.
0
1
ENUM
DISABLED
Disabled.The counters are disabled.
0
ENABLED
Enabled. The Timer Counter and Prescale Counter are
enabled.
1
CRST
Counter reset.
1
2
ENUM
DISABLED
Disabled. Do nothing.
0
ENABLED
Enabled. The Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of PCLK.
The counters remain reset until TCR[1] is returned to
zero.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
32
DMA
DMA controller
DMA
0x0
0x0
0x1000
registers
n
DMA
3
ABORT0
Channel Abort control for all DMA channels.
0x78
write-only
n
0x0
0x0
ABORTCTRL
Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.
0
22
RESERVED
Reserved.
22
32
ACTIVE0
Channel Active status for all DMA channels.
0x30
read-only
n
0x0
0x0
ACT
Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.
0
22
RESERVED
Reserved.
22
32
BUSY0
Channel Busy status for all DMA channels.
0x38
read-only
n
0x0
0x0
BSY
Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.
0
22
RESERVED
Reserved.
22
32
CFG0
Configuration register for DMA channel 0.
0x800
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG1
Configuration register for DMA channel 0.
0xC10
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG10
Configuration register for DMA channel 0.
0x3370
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG11
Configuration register for DMA channel 0.
0x3820
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG12
Configuration register for DMA channel 0.
0x3CE0
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG13
Configuration register for DMA channel 0.
0x41B0
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG14
Configuration register for DMA channel 0.
0x4690
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG15
Configuration register for DMA channel 0.
0x4B80
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG16
Configuration register for DMA channel 0.
0x5080
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG17
Configuration register for DMA channel 0.
0x5590
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG18
Configuration register for DMA channel 0.
0x5AB0
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG19
Configuration register for DMA channel 0.
0x5FE0
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG2
Configuration register for DMA channel 0.
0x1030
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG20
Configuration register for DMA channel 0.
0x6520
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG21
Configuration register for DMA channel 0.
0x6A70
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG3
Configuration register for DMA channel 0.
0x1460
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG4
Configuration register for DMA channel 0.
0x18A0
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG5
Configuration register for DMA channel 0.
0x1CF0
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG6
Configuration register for DMA channel 0.
0x2150
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG7
Configuration register for DMA channel 0.
0x25C0
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG8
Configuration register for DMA channel 0.
0x2A40
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CFG9
Configuration register for DMA channel 0.
0x2ED0
read-write
n
0x0
0x0
BURSTPOWER
Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
8
12
CHPRIORITY
Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
16
19
DSTBURSTWRAP
Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
15
16
ENUM
DISABLED
Disabled. Destination burst wrapping is not enabled
for this DMA channel.
0
ENABLED
Enabled. Destination burst wrapping is enabled for
this DMA channel.
1
HWTRIGEN
Hardware Triggering Enable for this channel.
1
2
ENUM
DISABLED
Disabled. Hardware triggering is not
used.
0
ENABLED
Enabled. Use hardware triggering.
1
PERIPHREQEN
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
0
1
ENUM
DISABLED
Disabled. Peripheral DMA requests are
disabled.
0
ENABLED
Enabled. Peripheral DMA requests are
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
14
SRCBURSTWRAP
Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
14
15
ENUM
DISABLED
Disabled. Source burst wrapping is not enabled for
this DMA channel.
0
ENABLED
Enabled. Source burst wrapping is enabled for this
DMA channel.
1
TRIGBURST
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
6
7
ENUM
SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single
transfer.
0
BURST_TRANSFER
Burst transfer. When the trigger for this channel
is set to edge triggered, a hardware trigger causes a burst
transfer, as defined by BURSTPOWER. When the trigger for
this channel is set to level triggered, a hardware trigger
causes transfers to continue as long as the trigger is
asserted, unless the transfer is complete.
1
TRIGPOL
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
4
5
ENUM
ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is
active low or falling edge triggered, based on
TRIGTYPE.
0
ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is
active high or rising edge triggered, based on
TRIGTYPE.
1
TRIGTYPE
Trigger Type. Selects hardware trigger as edge triggered or level triggered.
5
6
ENUM
EDGE
Edge. Hardware trigger is edge triggered. Transfers
will be initiated and completed, as specified for a single
trigger.
0
LEVEL
Level. Hardware trigger is level triggered. Note
that when level triggering without burst (BURSTPOWER = 0) is
selected, only hardware triggers should be used on that
channel. Transfers continue as long as the trigger level is
asserted. Once the trigger is de-asserted, the transfer will
be paused until the trigger is, again, asserted. However,
the transfer will not be paused until any remaining
transfers within the current BURSTPOWER length are
completed.
1
CTLSTAT0
Control and status register for DMA channel 0.
0x808
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT1
Control and status register for DMA channel 0.
0xC1C
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT10
Control and status register for DMA channel 0.
0x33A0
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT11
Control and status register for DMA channel 0.
0x3854
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT12
Control and status register for DMA channel 0.
0x3D18
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT13
Control and status register for DMA channel 0.
0x41EC
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT14
Control and status register for DMA channel 0.
0x46D0
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT15
Control and status register for DMA channel 0.
0x4BC4
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT16
Control and status register for DMA channel 0.
0x50C8
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT17
Control and status register for DMA channel 0.
0x55DC
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT18
Control and status register for DMA channel 0.
0x5B00
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT19
Control and status register for DMA channel 0.
0x6034
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT2
Control and status register for DMA channel 0.
0x1040
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT20
Control and status register for DMA channel 0.
0x6578
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT21
Control and status register for DMA channel 0.
0x6ACC
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT3
Control and status register for DMA channel 0.
0x1474
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT4
Control and status register for DMA channel 0.
0x18B8
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT5
Control and status register for DMA channel 0.
0x1D0C
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT6
Control and status register for DMA channel 0.
0x2170
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT7
Control and status register for DMA channel 0.
0x25E4
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT8
Control and status register for DMA channel 0.
0x2A68
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTLSTAT9
Control and status register for DMA channel 0.
0x2EFC
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
TRIG
Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
2
3
ENUM
NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is
not set. DMA operations will not be carried
out.
0
TRIGGERED
Triggered. The trigger for this DMA channel is set.
DMA operations will be carried out.
1
VALIDPENDING
Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
0
1
ENUM
NO_EFFECT
No effect. No effect on DMA
operation.
0
VALID_PENDING
Valid pending.
1
CTRL
DMA control.
0x0
read-write
n
0x0
0x0
ENABLE
DMA controller master enable.
0
1
ENUM
DISABLED
Disabled. The DMA controller is disabled. This
clears any triggers that were asserted at the point when
disabled, but does not prevent re-triggering when the DMA
controller is re-enabled.
0
ENABLED
Enabled. The DMA controller is
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
32
ENABLECLR0
Channel Enable Clear for all DMA channels.
0x28
write-only
n
0x0
0x0
CLR
Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.
0
22
RESERVED
Reserved.
22
32
ENABLESET0
Channel Enable read and Set for all DMA channels.
0x20
read-write
n
0x0
0x0
ENA
Enable for DMA channels. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.
0
22
RESERVED
Reserved. Read value is undefined, only zero should be written.
22
32
ERRINT0
Error Interrupt status for all DMA channels.
0x40
read-write
n
0x0
0x0
ERR
Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.
0
22
RESERVED
Reserved.
22
32
INTA0
Interrupt A status for all DMA channels.
0x58
read-write
n
0x0
0x0
IA
Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.
0
22
RESERVED
Reserved. Read value is undefined, only zero should be written.
22
32
INTB0
Interrupt B status for all DMA channels.
0x60
read-write
n
0x0
0x0
IB
Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.
0
22
RESERVED
Reserved. Read value is undefined, only zero should be written.
22
32
INTENCLR0
Interrupt Enable Clear for all DMA channels.
0x50
write-only
n
0x0
0x0
CLR
Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
0
22
RESERVED
Reserved.
22
32
INTENSET0
Interrupt Enable read and Set for all DMA channels.
0x48
read-write
n
0x0
0x0
INTEN
Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
0
22
RESERVED
Reserved.
22
32
INTSTAT
Interrupt status.
0x4
read-only
n
0x0
0x0
ACTIVEERRINT
Summarizes whether any error interrupts are pending.
2
3
ENUM
NOT_PENDING
Not pending. No error interrupts are
pending.
0
PENDING
Pending. At least one error interrupt is
pending.
1
ACTIVEINT
Summarizes whether any enabled interrupts (other than error interrupts) are pending.
1
2
ENUM
NOT_PENDING
Not pending. No enabled interrupts are
pending.
0
PENDING
Pending. At least one enabled interrupt is
pending.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
1
SETTRIG0
Set Trigger control bits for all DMA channels.
0x70
write-only
n
0x0
0x0
RESERVED
Reserved.
22
32
TRIG
Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.
0
22
SETVALID0
Set ValidPending control bits for all DMA channels.
0x68
write-only
n
0x0
0x0
RESERVED
Reserved.
22
32
SV
SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.
0
22
SRAMBASE
SRAM address of the channel configuration table.
0x8
read-write
n
0x0
0x0
OFFSET
Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary.
9
32
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
9
XFERCFG0
Transfer configuration register for DMA channel 0.
0x810
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG1
Transfer configuration register for DMA channel 0.
0xC28
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG10
Transfer configuration register for DMA channel 0.
0x33D0
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG11
Transfer configuration register for DMA channel 0.
0x3888
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG12
Transfer configuration register for DMA channel 0.
0x3D50
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG13
Transfer configuration register for DMA channel 0.
0x4228
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG14
Transfer configuration register for DMA channel 0.
0x4710
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG15
Transfer configuration register for DMA channel 0.
0x4C08
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG16
Transfer configuration register for DMA channel 0.
0x5110
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG17
Transfer configuration register for DMA channel 0.
0x5628
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG18
Transfer configuration register for DMA channel 0.
0x5B50
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG19
Transfer configuration register for DMA channel 0.
0x6088
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG2
Transfer configuration register for DMA channel 0.
0x1050
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG20
Transfer configuration register for DMA channel 0.
0x65D0
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG21
Transfer configuration register for DMA channel 0.
0x6B28
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG3
Transfer configuration register for DMA channel 0.
0x1488
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG4
Transfer configuration register for DMA channel 0.
0x18D0
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG5
Transfer configuration register for DMA channel 0.
0x1D28
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG6
Transfer configuration register for DMA channel 0.
0x2190
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG7
Transfer configuration register for DMA channel 0.
0x2608
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG8
Transfer configuration register for DMA channel 0.
0x2A90
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
XFERCFG9
Transfer configuration register for DMA channel 0.
0x2F28
read-write
n
0x0
0x0
CFGVALID
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
0
1
ENUM
NOT_VALID
Not valid. The channel descriptor is not considered
valid until validated by an associated SETVALID0
setting.
0
VALID
Valid. The current channel descriptor is considered
valid.
1
CLRTRIG
Clear Trigger.
3
4
ENUM
NOT_CLEARED
Not cleared. The trigger is not cleared when this
descriptor is exhausted. If there is a reload, the next
descriptor will be started.
0
CLEARED
Cleared. The trigger is cleared when this
descriptor is exhausted.
1
DSTINC
Determines whether the destination address is incremented for each DMA transfer.
14
16
ENUM
NO_INCREMENT
No increment. The destination address is not
incremented for each transfer. This is the usual case when
the destination is a peripheral device.
0x0
1_X_WIDTH
1 x width. The destination address is incremented
by the amount specified by Width for each transfer. This is
the usual case when the destination is memory.
0x1
2_X_WIDTH
2 x width. The destination address is incremented
by 2 times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The destination address is incremented
by 4 times the amount specified by Width for each
transfer.
0x3
RELOAD
Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1
2
ENUM
DISABLED
Disabled. Do not reload the channels' control
structure when the current descriptor is
exhausted.
0
ENABLED
Enabled. Reload the channels' control structure
when the current descriptor is exhausted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
12
SETINTA
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
4
5
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTA flag for this channel will be set
when the current descriptor is exhausted.
1
SETINTB
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
5
6
ENUM
NO_EFFECT
No effect.
0
SET
Set. The INTB flag for this channel will be set
when the current descriptor is exhausted.
1
SRCINC
Determines whether the source address is incremented for each DMA transfer.
12
14
ENUM
NO_INCREMENT
No increment. The source address is not incremented
for each transfer. This is the usual case when the source is
a peripheral device.
0x0
1_X_WIDTH
1 x width. The source address is incremented by the
amount specified by Width for each transfer. This is the
usual case when the source is memory.
0x1
2_X_WIDTH
2 x width. The source address is incremented by 2
times the amount specified by Width for each
transfer.
0x2
4_X_WIDTH
4 x width. The source address is incremented by 4
times the amount specified by Width for each
transfer.
0x3
SWTRIG
Software Trigger.
2
3
ENUM
NOT_SET
Not set. When written by software, the trigger for
this channel is not set. A new trigger, as defined by the
HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
channel.
0
SET
Set, When written by software, the trigger for this
channel is set immediately. This feature should not be used
with level triggering when TRIGBURST = 0.
1
WIDTH
Transfer width used for this DMA channel.
8
10
ENUM
8_BIT
8-bit. 8-bit transfers are performed (8-bit source
reads and destination writes).
0x0
16_BIT
16-bit. 6-bit transfers are performed (16-bit
source reads and destination writes).
0x1
32_BIT
32-bit. 32-bit transfers are performed (32-bit
source reads and destination writes).
0x2
RESERVED
Reserved. Reserved setting, do not
use.
0x3
XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
16
26
GINT0
Group GPIO input interrupt 0
GINT0
0x0
0x0
0x1000
registers
n
GINT0
4
CTRL
GPIO grouped interrupt control register
0x0
read-write
n
0x0
0x0
COMB
Combine enabled inputs for group interrupt
1
2
ENUM
OR
Or. OR functionality: A grouped interrupt is
generated when any one of the enabled inputs is active
(based on its programmed polarity).
0
AND
And. AND functionality: An interrupt is generated
when all enabled bits are active (based on their programmed
polarity).
1
INT
Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
0
1
ENUM
NO_REQUEST
No request. No interrupt request is
pending.
0
REQUEST_ACTIVE
Request active. Interrupt request is
active.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
32
TRIG
Group interrupt trigger
2
3
ENUM
EDGE_TRIGGERED
Edge-triggered.
0
LEVEL_TRIGGERED
Level-triggered.
1
PORT_ENA0
GPIO grouped interrupt port 0 enable register
0x80
read-write
n
0x0
0x0
ENA
Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
0
32
PORT_ENA1
GPIO grouped interrupt port 0 enable register
0xC4
read-write
n
0x0
0x0
ENA
Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
0
32
PORT_ENA2
GPIO grouped interrupt port 0 enable register
0x10C
read-write
n
0x0
0x0
ENA
Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
0
32
PORT_POL0
GPIO grouped interrupt port 0 polarity register
0x40
read-write
n
0x0
0x0
POL
Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
0
32
PORT_POL1
GPIO grouped interrupt port 0 polarity register
0x64
read-write
n
0x0
0x0
POL
Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
0
32
PORT_POL2
GPIO grouped interrupt port 0 polarity register
0x8C
read-write
n
0x0
0x0
POL
Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
0
32
GINT1
Group GPIO input interrupt 1
GINT0
0x0
0x0
0x1000
registers
n
GINT1
32
CTRL
GPIO grouped interrupt control register
0x0
read-write
n
0x0
0x0
COMB
Combine enabled inputs for group interrupt
1
2
ENUM
OR
Or. OR functionality: A grouped interrupt is
generated when any one of the enabled inputs is active
(based on its programmed polarity).
0
AND
And. AND functionality: An interrupt is generated
when all enabled bits are active (based on their programmed
polarity).
1
INT
Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
0
1
ENUM
NO_REQUEST
No request. No interrupt request is
pending.
0
REQUEST_ACTIVE
Request active. Interrupt request is
active.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
32
TRIG
Group interrupt trigger
2
3
ENUM
EDGE_TRIGGERED
Edge-triggered.
0
LEVEL_TRIGGERED
Level-triggered.
1
PORT_ENA0
GPIO grouped interrupt port 0 enable register
0x80
read-write
n
0x0
0x0
ENA
Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
0
32
PORT_ENA1
GPIO grouped interrupt port 0 enable register
0xC4
read-write
n
0x0
0x0
ENA
Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
0
32
PORT_ENA2
GPIO grouped interrupt port 0 enable register
0x10C
read-write
n
0x0
0x0
ENA
Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
0
32
PORT_POL0
GPIO grouped interrupt port 0 polarity register
0x40
read-write
n
0x0
0x0
POL
Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
0
32
PORT_POL1
GPIO grouped interrupt port 0 polarity register
0x64
read-write
n
0x0
0x0
POL
Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
0
32
PORT_POL2
GPIO grouped interrupt port 0 polarity register
0x8C
read-write
n
0x0
0x0
POL
Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
0
32
GPIO
General Purpose I/O
GPIO
0x0
0x0
0x2304
registers
n
B0
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x0
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B1
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B10
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x37
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B11
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x42
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B12
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x4E
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B13
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x5B
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B14
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x69
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B15
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x78
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B16
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x88
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B17
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x99
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B18
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0xAB
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B19
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0xBE
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B2
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x3
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B20
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0xD2
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B21
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0xE7
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B22
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0xFD
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B23
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x114
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B24
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x12C
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B25
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x145
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B26
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x15F
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B27
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x17A
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B28
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x196
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B29
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1B3
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B3
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x6
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B30
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1D1
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B31
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1F0
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B32
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x210
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B33
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x231
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B34
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x253
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B35
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x276
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B36
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x29A
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B37
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2BF
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B38
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2E5
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B39
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x30C
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B4
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0xA
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B40
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x334
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B41
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x35D
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B42
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x387
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B43
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x3B2
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B44
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x3DE
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B45
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x40B
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B46
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x439
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B47
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x468
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B48
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x498
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B49
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x4C9
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B5
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0xF
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B6
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x15
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B7
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1C
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B8
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x24
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
B9
Byte pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2D
1
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pins output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
CLR0
Clear port 0/1
0x4500
write-only
n
0x0
0x0
CLRP
Clear output bits. Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.
0
32
CLR1
Clear port 0/1
0x6784
write-only
n
0x0
0x0
CLRP
Clear output bits. Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.
0
32
DIR0
Direction registers port 0/1
0x4000
read-write
n
0x0
0x0
DIRP
Selects pin direction for pin PIOm_n. Supported pins depends on the specific device and package. 0 = input. 1 = output.
0
32
DIR1
Direction registers port 0/1
0x6004
read-write
n
0x0
0x0
DIRP
Selects pin direction for pin PIOm_n. Supported pins depends on the specific device and package. 0 = input. 1 = output.
0
32
MASK0
Mask register port 0/1
0x4100
read-write
n
0x0
0x0
MASKP
Controls which bits corresponding to PIOm_n are active in the MPORT register. Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.
0
32
MASK1
Mask register port 0/1
0x6184
read-write
n
0x0
0x0
MASKP
Controls which bits corresponding to PIOm_n are active in the MPORT register. Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.
0
32
MPIN0
Masked port register port 0/1
0x4300
read-write
n
0x0
0x0
MPORTP
Masked port register. Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.
0
32
MPIN1
Masked port register port 0/1
0x6484
read-write
n
0x0
0x0
MPORTP
Masked port register. Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.
0
32
NOT0
Toggle port 0/1
0x4600
write-only
n
0x0
0x0
NOTP
Toggle output bits. Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.
0
32
NOT1
Toggle port 0/1
0x6904
write-only
n
0x0
0x0
NOTP
Toggle output bits. Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.
0
32
PIN0
Port pin register port 0/1
0x4200
read-write
n
0x0
0x0
PORT
Reads pin states or loads output bits. Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.
0
32
PIN1
Port pin register port 0/1
0x6304
read-write
n
0x0
0x0
PORT
Reads pin states or loads output bits. Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.
0
32
SET0
Write: Set register for port 0/1 Read: output bits for port 0/1
0x4400
read-write
n
0x0
0x0
SETP
Read or set output bits. Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.
0
32
SET1
Write: Set register for port 0/1 Read: output bits for port 0/1
0x6604
read-write
n
0x0
0x0
SETP
Read or set output bits. Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.
0
32
W0
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2000
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W1
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x3004
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W10
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0xC0DC
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W11
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0xD108
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W12
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0xE138
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W13
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0xF16C
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W14
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x101A4
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W15
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x111E0
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W16
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x12220
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W17
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x13264
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W18
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x142AC
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W19
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x152F8
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W2
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x400C
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W20
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x16348
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W21
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1739C
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W22
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x183F4
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W23
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x19450
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W24
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1A4B0
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W25
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1B514
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W26
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1C57C
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W27
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1D5E8
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W28
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1E658
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W29
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x1F6CC
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W3
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x5018
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W30
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x20744
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W31
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x217C0
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W32
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x22840
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W33
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x238C4
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W34
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2494C
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W35
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x259D8
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W36
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x26A68
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W37
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x27AFC
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W38
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x28B94
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W39
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x29C30
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W4
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x6028
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W40
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2ACD0
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W41
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2BD74
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W42
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2CE1C
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W43
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2DEC8
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W44
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x2EF78
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W45
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x3002C
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W46
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x310E4
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W47
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x321A0
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W48
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x33260
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W49
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x34324
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W5
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x703C
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W6
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x8054
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W7
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0x9070
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W8
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0xA090
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
W9
Word pin registers port 0/1; pins PIO0_0 to PIO1_8
0xB0B4
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
I2C0
I2C-bus interface 0
I2C0
0x0
0x0
0x1000
registers
n
I2C0
21
CFG
Configuration for shared functions.
0x0
read-write
n
0x0
0x0
HSCAPABLE
High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: master, slave, and monitor.
5
6
ENUM
FAST_MODE_PLUS
Fast-mode plus. The I2C block will support
Standard-mode, Fast-mode, and Fast-mode Plus, to the extent
that the pin electronics support these modes. Any changes
that need to be made to the pin controls, such as changing
the drive strength or filtering, must be made by software
via the IOCON register associated with each I2C
pin,
0
HIGH_SPEED
High-speed. In addition to Standard-mode,
Fast-mode, and Fast-mode Plus, the I 2C block will support
High-speed mode to the extent that the pin electronics
support these modes. See Section 23.7.1.2 for more
information.
1
MONCLKSTR
Monitor function Clock Stretching.
4
5
ENUM
DISABLED
Disabled. The monitor function will not perform
clock stretching. Software or DMA may not always be able to
read data provided by the monitor function before it is
overwritten. This mode may be used when non-invasive
monitoring is critical.
0
ENABLED
Enabled. The monitor function will perform clock
stretching in order to ensure that software or DMA can read
all incoming data supplied by the monitor
function.
1
MONEN
Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.
2
3
ENUM
DISABLED
Disabled. The I2C monitor function is
disabled.
0
ENABLED
Enabled. The I2C monitor function is
enabled.
1
MSTEN
Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.
0
1
ENUM
DISABLED
Disabled. The I2C Master function is
disabled.
0
ENABLED
Enabled. The I2C Master function is
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
SLVEN
Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.
1
2
ENUM
DISABLED
Disabled. The I2C slave function is
disabled.
0
ENABLED
Enabled. The I2C slave function is
enabled.
1
TIMEOUTEN
I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
3
4
ENUM
DISABLED
Disabled. Time-out function is
disabled.
0
ENABLED
Enabled. Time-out function is enabled. Both types
of time-out flags will be generated and will cause
interrupts if they are enabled. Typically, only one time-out
will be used in a system.
1
CLKDIV
Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
0x14
read-write
n
0x0
0x0
DIVVAL
This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use. ... 0xFFFF = PCLK is divided by 65,536 before use.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
INTENCLR
Interrupt Enable Clear register.
0xC
write-only
n
0x0
0x0
EVENTTIMEOUTCLR
Event time-out interrupt clear.
24
25
MONIDLECLR
Monitor Idle interrupt clear.
19
20
MONOVCLR
Monitor Overrun interrupt clear.
17
18
MONRDYCLR
Monitor data Ready interrupt clear.
16
17
MSTARBLOSSCLR
Master Arbitration Loss interrupt clear.
4
5
MSTPENDINGCLR
Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
0
1
MSTSTSTPERRCLR
Master Start/Stop Error interrupt clear.
6
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUTCLR
SCL time-out interrupt clear.
25
26
SLVDESELCLR
Slave Deselect interrupt clear.
15
16
SLVNOTSTRCLR
Slave Not Stretching interrupt clear.
11
12
SLVPENDINGCLR
Slave Pending interrupt clear.
8
9
INTENSET
Interrupt Enable Set and read register.
0x8
read-write
n
0x0
0x0
EVENTTIMEOUTEN
Event time-out interrupt Enable.
24
25
ENUM
DISABLED
Disabled. The Event time-out interrupt is
disabled.
0
ENABLED
Enabled. The Event time-out interrupt is
enabled.
1
MONIDLEEN
Monitor Idle interrupt Enable.
19
20
ENUM
DISABLED
Disabled. The MonIdle interrupt is
disabled.
0
ENABLED
Enabled. The MonIdle interrupt is
enabled.
1
MONOVEN
Monitor Overrun interrupt Enable.
17
18
ENUM
DISABLED
Disabled. The MonOv interrupt is
disabled.
0
ENABLED
Enabled. The MonOv interrupt is
enabled.
1
MONRDYEN
Monitor data Ready interrupt Enable.
16
17
ENUM
DISABLED
Disabled. The MonRdy interrupt is
disabled.
0
ENABLED
Enabled. The MonRdy interrupt is
enabled.
1
MSTARBLOSSEN
Master Arbitration Loss interrupt Enable.
4
5
ENUM
DISABLED
Disabled. The MstArbLoss interrupt is
disabled.
0
ENABLED
Enabled. The MstArbLoss interrupt is
enabled.
1
MSTPENDINGEN
Master Pending interrupt Enable.
0
1
ENUM
DISABLED
Disabled. The MstPending interrupt is
disabled.
0
ENABLED
Enabled. The MstPending interrupt is
enabled.
1
MSTSTSTPERREN
Master Start/Stop Error interrupt Enable.
6
7
ENUM
DISABLED
Disabled. The MstStStpErr interrupt is
disabled.
0
ENABLED
Enabled. The MstStStpErr interrupt is
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUTEN
SCL time-out interrupt Enable.
25
26
ENUM
DISABLED
Disabled. The SCL time-out interrupt is
disabled.
0
ENABLED
Enabled. The SCL time-out interrupt is
enabled.
1
SLVDESELEN
Slave Deselect interrupt Enable.
15
16
ENUM
DISABLED
Disabled. The SlvDeSel interrupt is
disabled.
0
ENABLED
Enabled. The SlvDeSel interrupt is
enabled.
1
SLVNOTSTREN
Slave Not Stretching interrupt Enable.
11
12
ENUM
DISABLED
Disabled. The SlvNotStr interrupt is
disabled.
0
ENABLED
Enabled. The SlvNotStr interrupt is
enabled.
1
SLVPENDINGEN
Slave Pending interrupt Enable.
8
9
ENUM
DISABLED
Disabled. The SlvPending interrupt is
disabled.
0
ENABLED
Enabled. The SlvPending interrupt is
enabled.
1
INTSTAT
Interrupt Status register for Master, Slave, and Monitor functions.
0x18
read-only
n
0x0
0x0
EVENTTIMEOUT
Event time-out Interrupt flag.
24
25
MONIDLE
Monitor Idle flag.
19
20
MONOV
Monitor Overflow flag.
17
18
MONRDY
Monitor Ready.
16
17
MSTARBLOSS
Master Arbitration Loss flag.
4
5
MSTPENDING
Master Pending.
0
1
MSTSTSTPERR
Master Start/Stop Error flag.
6
7
RESERVED
Reserved.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUT
SCL time-out Interrupt flag.
25
26
SLVDESEL
Slave Deselected flag.
15
16
SLVNOTSTR
Slave Not Stretching status.
11
12
SLVPENDING
Slave Pending.
8
9
MONRXDAT
Monitor receiver data register.
0x80
read-only
n
0x0
0x0
MONNACK
Monitor Received NACK.
10
11
ENUM
ACKNOWLEDGED
Acknowledged. The data currently being provided by
the monitor function was acknowledged by at least one master
or slave receiver.
0
NOT_ACKNOWLEDGED
Not acknowledged. The data currently being provided
by the monitor function was not acknowledged by any
receiver.
1
MONRESTART
Monitor Received Repeated Start.
9
10
ENUM
NO_REPEATED_START_DE
No repeated start detected. The monitor function
has not detected a Repeated Start event on the I2C
bus.
0
REPEATED_START_DETEC
Repeated start detected. The monitor function has
detected a Repeated Start event on the I2C
bus.
1
MONRXDAT
Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
0
8
MONSTART
Monitor Received Start.
8
9
ENUM
NO_START_DETECTED
No start detected. The monitor function has not
detected a Start event on the I2C bus.
0
START_DETECTED
Start detected. The monitor function has detected a
Start event on the I2C bus.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
11
32
MSTCTL
Master control register.
0x20
read-write
n
0x0
0x0
MSTCONTINUE
Master Continue. This bit is write-only.
0
1
ENUM
NO_EFFECT
No effect.
0
CONTINUE
Continue. Informs the Master function to continue
to the next operation. This must done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.
1
MSTDMA
Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.
3
4
ENUM
DISABLE
Disable. No DMA requests are generated for master
operation.
0
ENABLE
Enable. A DMA request is generated for I2C master
data operations. When this I2C master is generating
Acknowledge bits in Master Receiver mode, the acknowledge is
generated automatically.
1
MSTSTART
Master Start control. This bit is write-only.
1
2
ENUM
NO_EFFECT
No effect.
0
START
Start. A Start will be generated on the I2C bus at
the next allowed time.
1
MSTSTOP
Master Stop control. This bit is write-only.
2
3
ENUM
NO_EFFECT
No effect.
0
STOP
Stop. A Stop will be generated on the I2C bus at
the next allowed time, preceded by a NACK to the slave if
the master is receiving data from the slave (Master Receiver
mode).
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
MSTDAT
Combined Master receiver and transmitter data register.
0x28
read-write
n
0x0
0x0
DATA
Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
MSTTIME
Master timing configuration.
0x24
read-write
n
0x0
0x0
MSTSCLHIGH
Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
4
7
ENUM
2_CLOCKS
2 clocks. Minimum SCL high time is 2 clock of the
I2C clock pre-divider.
0x0
3_CLOCKS
3 clocks. Minimum SCL high time is 3 clocks of the
I2C clock pre-divider .
0x1
4_CLOCKS
4 clocks. Minimum SCL high time is 4 clock of the
I2C clock pre-divider.
0x2
5_CLOCKS
5 clocks. Minimum SCL high time is 5 clock of the
I2C clock pre-divider.
0x3
6_CLOCKS
6 clocks. Minimum SCL high time is 6 clock of the
I2C clock pre-divider.
0x4
7_CLOCKS
7 clocks. Minimum SCL high time is 7 clock of the
I2C clock pre-divider.
0x5
8_CLOCKS
8 clocks. Minimum SCL high time is 8 clock of the
I2C clock pre-divider.
0x6
9_CLOCKS
9 clocks. Minimum SCL high time is 9 clocks of the
I2C clock pre-divider.
0x7
MSTSCLLOW
Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus specification parameters tBUF and t SU;STA have the same values and are also controlled by MSTSCLLOW.
0
3
ENUM
2_CLOCKS
2 clocks. Minimum SCL low time is 2 clocks of the
I2C clock pre-divider.
0x0
3_CLOCKS
3 clocks. Minimum SCL low time is 3 clocks of the
I2C clock pre-divider.
0x1
4_CLOCKS
4 clocks. Minimum SCL low time is 4 clocks of the
I2C clock pre-divider.
0x2
5_CLOCKS
5 clocks. Minimum SCL low time is 5 clocks of the
I2C clock pre-divider.
0x3
6_CLOCKS
6 clocks. Minimum SCL low time is 6 clocks of the
I2C clock pre-divider.
0x4
7_CLOCKS
7 clocks. Minimum SCL low time is 7 clocks of the
I2C clock pre-divider.
0x5
8_CLOCKS
8 clocks. Minimum SCL low time is 8 clocks of the
I2C clock pre-divider.
0x6
9_CLOCKS
9 clocks. Minimum SCL low time is 9 clocks of the
I2C clock pre-divider.
0x7
RESERVED
Reserved.
3
4
RESERVED
Reserved.
3
4
SLVADR0
Slave address 0.
0x90
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR1
Slave address 0.
0xDC
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR2
Slave address 0.
0x12C
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR3
Slave address 0.
0x180
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVCTL
Slave control register.
0x40
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
SLVCONTINUE
Slave Continue.
0
1
ENUM
NO_EFFECT
No effect.
0
CONTINUE
Continue. Informs the Slave function to continue to
the next operation. This must be done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.
1
SLVDMA
Slave DMA enable.
3
4
ENUM
DISABLED
Disabled. No DMA requests are issued for Slave mode
operation.
0
ENABLED
Enabled. DMA requests are issued for I2C slave data
transmission and reception.
1
SLVNACK
Slave NACK.
1
2
ENUM
NO_EFFECT
No effect.
0
NACK
NACK. Causes the Slave function to NACK the master
when the slave is receiving data from the master (Slave
Receiver mode).
1
SLVDAT
Combined Slave receiver and transmitter data register.
0x44
read-write
n
0x0
0x0
DATA
Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SLVQUAL0
Slave Qualification for address 0.
0x58
read-write
n
0x0
0x0
QUALMODE0
Qualify mode for slave address 0.
0
1
ENUM
MASK
Mask. The SLVQUAL0 field is used as a logical mask
for matching address 0.
0
EXTEND
Extend. The SLVQUAL0 field is used to extend
address 0 matching in a range of addresses.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SLVQUAL0
Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
1
8
STAT
Status register for Master, Slave, and Monitor functions.
0x4
read-write
n
0x0
0x0
EVENTTIMEOUT
Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.
24
25
ENUM
NO_TIME_OUT
No time-out. I2C bus events have not caused a
time-out.
0
EVENT_TIME_OUT
Event time-out. The time between I2C bus events has
been longer than the time specified by the I2C TIMEOUT
register.
1
MONACTIVE
Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.
18
19
ENUM
INACTIVE
Inactive. The Monitor function considers the I2C
bus to be inactive.
0
ACTIVE
Active. The Monitor function considers the I2C bus
to be active.
1
MONIDLE
Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.
19
20
ENUM
NOT_IDLE
Not idle. The I2C bus is not idle, or this flag has
been cleared by software.
0
IDLE
Idle. The I2C bus has gone idle at least once since
the last time this flag was cleared by
software.
1
MONOV
Monitor Overflow flag.
17
18
ENUM
NO_OVERRUN
No overrun. Monitor data has not
overrun.
0
OVERRUN
Overrun. A Monitor data overrun has occurred. This
can only happen when Monitor clock stretching not enabled
via the MONCLKSTR bit in the CFG register. Writing 1 to this
bit clears the flag.
1
MONRDY
Monitor Ready. This flag is cleared when the MONRXDAT register is read.
16
17
ENUM
NO_DATA
No data. The Monitor function does not currently
have data available.
0
DATA_WAITING
Data waiting. The Monitor function has data waiting
to be read.
1
MSTARBLOSS
Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
4
5
ENUM
NO_ARBITRATION_LOSS
No Arbitration Loss has occurred.
0
ARBITRATION_LOSS
Arbitration loss. The Master function has
experienced an Arbitration Loss. At this point, the Master
function has already stopped driving the bus and gone to an
idle state. Software can respond by doing nothing, or by
sending a Start in order to attempt to gain control of the
bus when it next becomes idle.
1
MSTPENDING
Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.
0
1
ENUM
IN_PROGRESS
In progress. Communication is in progress and the
Master function is busy and cannot currently accept a
command.
0
PENDING
Pending. The Master function needs software service
or is in the idle state. If the master is not in the idle
state, it is waiting to receive or transmit data or the NACK
bit.
1
MSTSTATE
Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 346 for details of state values and appropriate responses.
1
4
ENUM
IDLE
Idle. The Master function is available to be used
for a new transaction.
0x0
RECEIVE_READY
Receive ready. Received data available (Master
Receiver mode). Address plus Read was previously sent and
Acknowledged by slave.
0x1
TRANSMIT_READY
Transmit ready. Data can be transmitted (Master
Transmitter mode). Address plus Write was previously sent
and Acknowledged by slave.
0x2
NACK_ADDRESS
NACK Address. Slave NACKed address.
0x3
NACK_DATA
NACK Data. Slave NACKed transmitted
data.
0x4
MSTSTSTPERR
Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
6
7
ENUM
NO_STARTSTOP_ERROR
No Start/Stop Error has occurred.
0
THE_MASTER_FUNCTION
The Master function has experienced a Start/Stop
Error. A Start or Stop was detected at a time when it is not
allowed by the I2C specification. The Master interface has
stopped driving the bus and gone to an idle state, no action
is required. A request for a Start could be made, or
software could attempt to insure that the bus has not
stalled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUT
SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
25
26
ENUM
NO_TIME_OUT
No time-out. SCL low time has not caused a
time-out.
0
TIME_OUT
Time-out. SCL low time has caused a
time-out.
1
SLVDESEL
Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.
15
16
ENUM
NOT_DESELECTED
Not deselected. The Slave function has not become
deselected. This does not mean that it is currently
selected. That information can be found in the SLVSEL
flag.
0
DESELECTED
Deselected. The Slave function has become
deselected. This is specifically caused by the SLVSEL flag
changing from 1 to 0. See the description of SLVSEL for
details on when that event occurs.
1
SLVIDX
Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.
12
14
ENUM
ADDRESS_0
Address 0. Slave address 0 was
matched.
0x0
ADDRESS_1
Address 1. Slave address 1 was
matched.
0x1
ADDRESS_2
Address 2. Slave address 2 was
matched.
0x2
ADDRESS_3
Address 3. Slave address 3 was
matched.
0x3
SLVNOTSTR
Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.
11
12
ENUM
STRETCHING
Stretching. The slave function is currently
stretching the I2C bus clock. Deep-Sleep or Power-down mode
cannot be entered at this time.
0
NOT_STRETCHING
Not stretching. The slave function is not currently
stretching the I 2C bus clock. Deep-sleep or Power-down mode
could be entered at this time.
1
SLVPENDING
Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register. The point in time when SlvPending is set depends on whether the I2C block is in HSCAPABLE mode. See Section 23.7.1.2.2. When the I2C block is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.
8
9
ENUM
IN_PROGRESS
In progress. The Slave function does not currently
need service.
0
PENDING
Pending. The Slave function needs service.
Information on what is needed can be found in the adjacent
SLVSTATE field.
1
SLVSEL
Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software NACKs data.
14
15
ENUM
NOT_SELECTED
Not selected. The Slave function is not currently
selected.
0
SELECTED
Selected. The Slave function is currently
selected.
1
SLVSTATE
Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions.
9
11
ENUM
SLAVE_ADDRESS
Slave address. Address plus R/W received. At least
one of the four slave addresses has been matched by
hardware.
0x0
SLAVE_RECEIVE
Slave receive. Received data is available (Slave
Receiver mode).
0x1
SLAVE_TRANSMIT
Slave transmit. Data can be transmitted (Slave
Transmitter mode).
0x2
TIMEOUT
Time-out value register.
0x10
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
TO
Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks, as defined by the CLKDIV register. To change this value while I 2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. ... 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.
4
16
TOMIN
Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
0
4
I2C1
I2C-bus interface 1
I2C0
0x0
0x0
0x1000
registers
n
I2C1
22
CFG
Configuration for shared functions.
0x0
read-write
n
0x0
0x0
HSCAPABLE
High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: master, slave, and monitor.
5
6
ENUM
FAST_MODE_PLUS
Fast-mode plus. The I2C block will support
Standard-mode, Fast-mode, and Fast-mode Plus, to the extent
that the pin electronics support these modes. Any changes
that need to be made to the pin controls, such as changing
the drive strength or filtering, must be made by software
via the IOCON register associated with each I2C
pin,
0
HIGH_SPEED
High-speed. In addition to Standard-mode,
Fast-mode, and Fast-mode Plus, the I 2C block will support
High-speed mode to the extent that the pin electronics
support these modes. See Section 23.7.1.2 for more
information.
1
MONCLKSTR
Monitor function Clock Stretching.
4
5
ENUM
DISABLED
Disabled. The monitor function will not perform
clock stretching. Software or DMA may not always be able to
read data provided by the monitor function before it is
overwritten. This mode may be used when non-invasive
monitoring is critical.
0
ENABLED
Enabled. The monitor function will perform clock
stretching in order to ensure that software or DMA can read
all incoming data supplied by the monitor
function.
1
MONEN
Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.
2
3
ENUM
DISABLED
Disabled. The I2C monitor function is
disabled.
0
ENABLED
Enabled. The I2C monitor function is
enabled.
1
MSTEN
Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.
0
1
ENUM
DISABLED
Disabled. The I2C Master function is
disabled.
0
ENABLED
Enabled. The I2C Master function is
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
SLVEN
Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.
1
2
ENUM
DISABLED
Disabled. The I2C slave function is
disabled.
0
ENABLED
Enabled. The I2C slave function is
enabled.
1
TIMEOUTEN
I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
3
4
ENUM
DISABLED
Disabled. Time-out function is
disabled.
0
ENABLED
Enabled. Time-out function is enabled. Both types
of time-out flags will be generated and will cause
interrupts if they are enabled. Typically, only one time-out
will be used in a system.
1
CLKDIV
Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
0x14
read-write
n
0x0
0x0
DIVVAL
This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use. ... 0xFFFF = PCLK is divided by 65,536 before use.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
INTENCLR
Interrupt Enable Clear register.
0xC
write-only
n
0x0
0x0
EVENTTIMEOUTCLR
Event time-out interrupt clear.
24
25
MONIDLECLR
Monitor Idle interrupt clear.
19
20
MONOVCLR
Monitor Overrun interrupt clear.
17
18
MONRDYCLR
Monitor data Ready interrupt clear.
16
17
MSTARBLOSSCLR
Master Arbitration Loss interrupt clear.
4
5
MSTPENDINGCLR
Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
0
1
MSTSTSTPERRCLR
Master Start/Stop Error interrupt clear.
6
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUTCLR
SCL time-out interrupt clear.
25
26
SLVDESELCLR
Slave Deselect interrupt clear.
15
16
SLVNOTSTRCLR
Slave Not Stretching interrupt clear.
11
12
SLVPENDINGCLR
Slave Pending interrupt clear.
8
9
INTENSET
Interrupt Enable Set and read register.
0x8
read-write
n
0x0
0x0
EVENTTIMEOUTEN
Event time-out interrupt Enable.
24
25
ENUM
DISABLED
Disabled. The Event time-out interrupt is
disabled.
0
ENABLED
Enabled. The Event time-out interrupt is
enabled.
1
MONIDLEEN
Monitor Idle interrupt Enable.
19
20
ENUM
DISABLED
Disabled. The MonIdle interrupt is
disabled.
0
ENABLED
Enabled. The MonIdle interrupt is
enabled.
1
MONOVEN
Monitor Overrun interrupt Enable.
17
18
ENUM
DISABLED
Disabled. The MonOv interrupt is
disabled.
0
ENABLED
Enabled. The MonOv interrupt is
enabled.
1
MONRDYEN
Monitor data Ready interrupt Enable.
16
17
ENUM
DISABLED
Disabled. The MonRdy interrupt is
disabled.
0
ENABLED
Enabled. The MonRdy interrupt is
enabled.
1
MSTARBLOSSEN
Master Arbitration Loss interrupt Enable.
4
5
ENUM
DISABLED
Disabled. The MstArbLoss interrupt is
disabled.
0
ENABLED
Enabled. The MstArbLoss interrupt is
enabled.
1
MSTPENDINGEN
Master Pending interrupt Enable.
0
1
ENUM
DISABLED
Disabled. The MstPending interrupt is
disabled.
0
ENABLED
Enabled. The MstPending interrupt is
enabled.
1
MSTSTSTPERREN
Master Start/Stop Error interrupt Enable.
6
7
ENUM
DISABLED
Disabled. The MstStStpErr interrupt is
disabled.
0
ENABLED
Enabled. The MstStStpErr interrupt is
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUTEN
SCL time-out interrupt Enable.
25
26
ENUM
DISABLED
Disabled. The SCL time-out interrupt is
disabled.
0
ENABLED
Enabled. The SCL time-out interrupt is
enabled.
1
SLVDESELEN
Slave Deselect interrupt Enable.
15
16
ENUM
DISABLED
Disabled. The SlvDeSel interrupt is
disabled.
0
ENABLED
Enabled. The SlvDeSel interrupt is
enabled.
1
SLVNOTSTREN
Slave Not Stretching interrupt Enable.
11
12
ENUM
DISABLED
Disabled. The SlvNotStr interrupt is
disabled.
0
ENABLED
Enabled. The SlvNotStr interrupt is
enabled.
1
SLVPENDINGEN
Slave Pending interrupt Enable.
8
9
ENUM
DISABLED
Disabled. The SlvPending interrupt is
disabled.
0
ENABLED
Enabled. The SlvPending interrupt is
enabled.
1
INTSTAT
Interrupt Status register for Master, Slave, and Monitor functions.
0x18
read-only
n
0x0
0x0
EVENTTIMEOUT
Event time-out Interrupt flag.
24
25
MONIDLE
Monitor Idle flag.
19
20
MONOV
Monitor Overflow flag.
17
18
MONRDY
Monitor Ready.
16
17
MSTARBLOSS
Master Arbitration Loss flag.
4
5
MSTPENDING
Master Pending.
0
1
MSTSTSTPERR
Master Start/Stop Error flag.
6
7
RESERVED
Reserved.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUT
SCL time-out Interrupt flag.
25
26
SLVDESEL
Slave Deselected flag.
15
16
SLVNOTSTR
Slave Not Stretching status.
11
12
SLVPENDING
Slave Pending.
8
9
MONRXDAT
Monitor receiver data register.
0x80
read-only
n
0x0
0x0
MONNACK
Monitor Received NACK.
10
11
ENUM
ACKNOWLEDGED
Acknowledged. The data currently being provided by
the monitor function was acknowledged by at least one master
or slave receiver.
0
NOT_ACKNOWLEDGED
Not acknowledged. The data currently being provided
by the monitor function was not acknowledged by any
receiver.
1
MONRESTART
Monitor Received Repeated Start.
9
10
ENUM
NO_REPEATED_START_DE
No repeated start detected. The monitor function
has not detected a Repeated Start event on the I2C
bus.
0
REPEATED_START_DETEC
Repeated start detected. The monitor function has
detected a Repeated Start event on the I2C
bus.
1
MONRXDAT
Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
0
8
MONSTART
Monitor Received Start.
8
9
ENUM
NO_START_DETECTED
No start detected. The monitor function has not
detected a Start event on the I2C bus.
0
START_DETECTED
Start detected. The monitor function has detected a
Start event on the I2C bus.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
11
32
MSTCTL
Master control register.
0x20
read-write
n
0x0
0x0
MSTCONTINUE
Master Continue. This bit is write-only.
0
1
ENUM
NO_EFFECT
No effect.
0
CONTINUE
Continue. Informs the Master function to continue
to the next operation. This must done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.
1
MSTDMA
Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.
3
4
ENUM
DISABLE
Disable. No DMA requests are generated for master
operation.
0
ENABLE
Enable. A DMA request is generated for I2C master
data operations. When this I2C master is generating
Acknowledge bits in Master Receiver mode, the acknowledge is
generated automatically.
1
MSTSTART
Master Start control. This bit is write-only.
1
2
ENUM
NO_EFFECT
No effect.
0
START
Start. A Start will be generated on the I2C bus at
the next allowed time.
1
MSTSTOP
Master Stop control. This bit is write-only.
2
3
ENUM
NO_EFFECT
No effect.
0
STOP
Stop. A Stop will be generated on the I2C bus at
the next allowed time, preceded by a NACK to the slave if
the master is receiving data from the slave (Master Receiver
mode).
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
MSTDAT
Combined Master receiver and transmitter data register.
0x28
read-write
n
0x0
0x0
DATA
Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
MSTTIME
Master timing configuration.
0x24
read-write
n
0x0
0x0
MSTSCLHIGH
Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
4
7
ENUM
2_CLOCKS
2 clocks. Minimum SCL high time is 2 clock of the
I2C clock pre-divider.
0x0
3_CLOCKS
3 clocks. Minimum SCL high time is 3 clocks of the
I2C clock pre-divider .
0x1
4_CLOCKS
4 clocks. Minimum SCL high time is 4 clock of the
I2C clock pre-divider.
0x2
5_CLOCKS
5 clocks. Minimum SCL high time is 5 clock of the
I2C clock pre-divider.
0x3
6_CLOCKS
6 clocks. Minimum SCL high time is 6 clock of the
I2C clock pre-divider.
0x4
7_CLOCKS
7 clocks. Minimum SCL high time is 7 clock of the
I2C clock pre-divider.
0x5
8_CLOCKS
8 clocks. Minimum SCL high time is 8 clock of the
I2C clock pre-divider.
0x6
9_CLOCKS
9 clocks. Minimum SCL high time is 9 clocks of the
I2C clock pre-divider.
0x7
MSTSCLLOW
Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus specification parameters tBUF and t SU;STA have the same values and are also controlled by MSTSCLLOW.
0
3
ENUM
2_CLOCKS
2 clocks. Minimum SCL low time is 2 clocks of the
I2C clock pre-divider.
0x0
3_CLOCKS
3 clocks. Minimum SCL low time is 3 clocks of the
I2C clock pre-divider.
0x1
4_CLOCKS
4 clocks. Minimum SCL low time is 4 clocks of the
I2C clock pre-divider.
0x2
5_CLOCKS
5 clocks. Minimum SCL low time is 5 clocks of the
I2C clock pre-divider.
0x3
6_CLOCKS
6 clocks. Minimum SCL low time is 6 clocks of the
I2C clock pre-divider.
0x4
7_CLOCKS
7 clocks. Minimum SCL low time is 7 clocks of the
I2C clock pre-divider.
0x5
8_CLOCKS
8 clocks. Minimum SCL low time is 8 clocks of the
I2C clock pre-divider.
0x6
9_CLOCKS
9 clocks. Minimum SCL low time is 9 clocks of the
I2C clock pre-divider.
0x7
RESERVED
Reserved.
3
4
RESERVED
Reserved.
3
4
SLVADR0
Slave address 0.
0x90
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR1
Slave address 0.
0xDC
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR2
Slave address 0.
0x12C
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR3
Slave address 0.
0x180
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVCTL
Slave control register.
0x40
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
SLVCONTINUE
Slave Continue.
0
1
ENUM
NO_EFFECT
No effect.
0
CONTINUE
Continue. Informs the Slave function to continue to
the next operation. This must be done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.
1
SLVDMA
Slave DMA enable.
3
4
ENUM
DISABLED
Disabled. No DMA requests are issued for Slave mode
operation.
0
ENABLED
Enabled. DMA requests are issued for I2C slave data
transmission and reception.
1
SLVNACK
Slave NACK.
1
2
ENUM
NO_EFFECT
No effect.
0
NACK
NACK. Causes the Slave function to NACK the master
when the slave is receiving data from the master (Slave
Receiver mode).
1
SLVDAT
Combined Slave receiver and transmitter data register.
0x44
read-write
n
0x0
0x0
DATA
Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SLVQUAL0
Slave Qualification for address 0.
0x58
read-write
n
0x0
0x0
QUALMODE0
Qualify mode for slave address 0.
0
1
ENUM
MASK
Mask. The SLVQUAL0 field is used as a logical mask
for matching address 0.
0
EXTEND
Extend. The SLVQUAL0 field is used to extend
address 0 matching in a range of addresses.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SLVQUAL0
Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
1
8
STAT
Status register for Master, Slave, and Monitor functions.
0x4
read-write
n
0x0
0x0
EVENTTIMEOUT
Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.
24
25
ENUM
NO_TIME_OUT
No time-out. I2C bus events have not caused a
time-out.
0
EVENT_TIME_OUT
Event time-out. The time between I2C bus events has
been longer than the time specified by the I2C TIMEOUT
register.
1
MONACTIVE
Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.
18
19
ENUM
INACTIVE
Inactive. The Monitor function considers the I2C
bus to be inactive.
0
ACTIVE
Active. The Monitor function considers the I2C bus
to be active.
1
MONIDLE
Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.
19
20
ENUM
NOT_IDLE
Not idle. The I2C bus is not idle, or this flag has
been cleared by software.
0
IDLE
Idle. The I2C bus has gone idle at least once since
the last time this flag was cleared by
software.
1
MONOV
Monitor Overflow flag.
17
18
ENUM
NO_OVERRUN
No overrun. Monitor data has not
overrun.
0
OVERRUN
Overrun. A Monitor data overrun has occurred. This
can only happen when Monitor clock stretching not enabled
via the MONCLKSTR bit in the CFG register. Writing 1 to this
bit clears the flag.
1
MONRDY
Monitor Ready. This flag is cleared when the MONRXDAT register is read.
16
17
ENUM
NO_DATA
No data. The Monitor function does not currently
have data available.
0
DATA_WAITING
Data waiting. The Monitor function has data waiting
to be read.
1
MSTARBLOSS
Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
4
5
ENUM
NO_ARBITRATION_LOSS
No Arbitration Loss has occurred.
0
ARBITRATION_LOSS
Arbitration loss. The Master function has
experienced an Arbitration Loss. At this point, the Master
function has already stopped driving the bus and gone to an
idle state. Software can respond by doing nothing, or by
sending a Start in order to attempt to gain control of the
bus when it next becomes idle.
1
MSTPENDING
Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.
0
1
ENUM
IN_PROGRESS
In progress. Communication is in progress and the
Master function is busy and cannot currently accept a
command.
0
PENDING
Pending. The Master function needs software service
or is in the idle state. If the master is not in the idle
state, it is waiting to receive or transmit data or the NACK
bit.
1
MSTSTATE
Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 346 for details of state values and appropriate responses.
1
4
ENUM
IDLE
Idle. The Master function is available to be used
for a new transaction.
0x0
RECEIVE_READY
Receive ready. Received data available (Master
Receiver mode). Address plus Read was previously sent and
Acknowledged by slave.
0x1
TRANSMIT_READY
Transmit ready. Data can be transmitted (Master
Transmitter mode). Address plus Write was previously sent
and Acknowledged by slave.
0x2
NACK_ADDRESS
NACK Address. Slave NACKed address.
0x3
NACK_DATA
NACK Data. Slave NACKed transmitted
data.
0x4
MSTSTSTPERR
Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
6
7
ENUM
NO_STARTSTOP_ERROR
No Start/Stop Error has occurred.
0
THE_MASTER_FUNCTION
The Master function has experienced a Start/Stop
Error. A Start or Stop was detected at a time when it is not
allowed by the I2C specification. The Master interface has
stopped driving the bus and gone to an idle state, no action
is required. A request for a Start could be made, or
software could attempt to insure that the bus has not
stalled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUT
SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
25
26
ENUM
NO_TIME_OUT
No time-out. SCL low time has not caused a
time-out.
0
TIME_OUT
Time-out. SCL low time has caused a
time-out.
1
SLVDESEL
Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.
15
16
ENUM
NOT_DESELECTED
Not deselected. The Slave function has not become
deselected. This does not mean that it is currently
selected. That information can be found in the SLVSEL
flag.
0
DESELECTED
Deselected. The Slave function has become
deselected. This is specifically caused by the SLVSEL flag
changing from 1 to 0. See the description of SLVSEL for
details on when that event occurs.
1
SLVIDX
Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.
12
14
ENUM
ADDRESS_0
Address 0. Slave address 0 was
matched.
0x0
ADDRESS_1
Address 1. Slave address 1 was
matched.
0x1
ADDRESS_2
Address 2. Slave address 2 was
matched.
0x2
ADDRESS_3
Address 3. Slave address 3 was
matched.
0x3
SLVNOTSTR
Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.
11
12
ENUM
STRETCHING
Stretching. The slave function is currently
stretching the I2C bus clock. Deep-Sleep or Power-down mode
cannot be entered at this time.
0
NOT_STRETCHING
Not stretching. The slave function is not currently
stretching the I 2C bus clock. Deep-sleep or Power-down mode
could be entered at this time.
1
SLVPENDING
Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register. The point in time when SlvPending is set depends on whether the I2C block is in HSCAPABLE mode. See Section 23.7.1.2.2. When the I2C block is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.
8
9
ENUM
IN_PROGRESS
In progress. The Slave function does not currently
need service.
0
PENDING
Pending. The Slave function needs service.
Information on what is needed can be found in the adjacent
SLVSTATE field.
1
SLVSEL
Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software NACKs data.
14
15
ENUM
NOT_SELECTED
Not selected. The Slave function is not currently
selected.
0
SELECTED
Selected. The Slave function is currently
selected.
1
SLVSTATE
Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions.
9
11
ENUM
SLAVE_ADDRESS
Slave address. Address plus R/W received. At least
one of the four slave addresses has been matched by
hardware.
0x0
SLAVE_RECEIVE
Slave receive. Received data is available (Slave
Receiver mode).
0x1
SLAVE_TRANSMIT
Slave transmit. Data can be transmitted (Slave
Transmitter mode).
0x2
TIMEOUT
Time-out value register.
0x10
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
TO
Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks, as defined by the CLKDIV register. To change this value while I 2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. ... 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.
4
16
TOMIN
Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
0
4
I2C2
I2C-bus interface 2
I2C0
0x0
0x0
0x1000
registers
n
I2C2
23
CFG
Configuration for shared functions.
0x0
read-write
n
0x0
0x0
HSCAPABLE
High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: master, slave, and monitor.
5
6
ENUM
FAST_MODE_PLUS
Fast-mode plus. The I2C block will support
Standard-mode, Fast-mode, and Fast-mode Plus, to the extent
that the pin electronics support these modes. Any changes
that need to be made to the pin controls, such as changing
the drive strength or filtering, must be made by software
via the IOCON register associated with each I2C
pin,
0
HIGH_SPEED
High-speed. In addition to Standard-mode,
Fast-mode, and Fast-mode Plus, the I 2C block will support
High-speed mode to the extent that the pin electronics
support these modes. See Section 23.7.1.2 for more
information.
1
MONCLKSTR
Monitor function Clock Stretching.
4
5
ENUM
DISABLED
Disabled. The monitor function will not perform
clock stretching. Software or DMA may not always be able to
read data provided by the monitor function before it is
overwritten. This mode may be used when non-invasive
monitoring is critical.
0
ENABLED
Enabled. The monitor function will perform clock
stretching in order to ensure that software or DMA can read
all incoming data supplied by the monitor
function.
1
MONEN
Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.
2
3
ENUM
DISABLED
Disabled. The I2C monitor function is
disabled.
0
ENABLED
Enabled. The I2C monitor function is
enabled.
1
MSTEN
Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.
0
1
ENUM
DISABLED
Disabled. The I2C Master function is
disabled.
0
ENABLED
Enabled. The I2C Master function is
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
SLVEN
Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.
1
2
ENUM
DISABLED
Disabled. The I2C slave function is
disabled.
0
ENABLED
Enabled. The I2C slave function is
enabled.
1
TIMEOUTEN
I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
3
4
ENUM
DISABLED
Disabled. Time-out function is
disabled.
0
ENABLED
Enabled. Time-out function is enabled. Both types
of time-out flags will be generated and will cause
interrupts if they are enabled. Typically, only one time-out
will be used in a system.
1
CLKDIV
Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
0x14
read-write
n
0x0
0x0
DIVVAL
This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = PCLK is used directly by the I2C. 0x0001 = PCLK is divided by 2 before use. 0x0002 = PCLK is divided by 3 before use. ... 0xFFFF = PCLK is divided by 65,536 before use.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
INTENCLR
Interrupt Enable Clear register.
0xC
write-only
n
0x0
0x0
EVENTTIMEOUTCLR
Event time-out interrupt clear.
24
25
MONIDLECLR
Monitor Idle interrupt clear.
19
20
MONOVCLR
Monitor Overrun interrupt clear.
17
18
MONRDYCLR
Monitor data Ready interrupt clear.
16
17
MSTARBLOSSCLR
Master Arbitration Loss interrupt clear.
4
5
MSTPENDINGCLR
Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
0
1
MSTSTSTPERRCLR
Master Start/Stop Error interrupt clear.
6
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUTCLR
SCL time-out interrupt clear.
25
26
SLVDESELCLR
Slave Deselect interrupt clear.
15
16
SLVNOTSTRCLR
Slave Not Stretching interrupt clear.
11
12
SLVPENDINGCLR
Slave Pending interrupt clear.
8
9
INTENSET
Interrupt Enable Set and read register.
0x8
read-write
n
0x0
0x0
EVENTTIMEOUTEN
Event time-out interrupt Enable.
24
25
ENUM
DISABLED
Disabled. The Event time-out interrupt is
disabled.
0
ENABLED
Enabled. The Event time-out interrupt is
enabled.
1
MONIDLEEN
Monitor Idle interrupt Enable.
19
20
ENUM
DISABLED
Disabled. The MonIdle interrupt is
disabled.
0
ENABLED
Enabled. The MonIdle interrupt is
enabled.
1
MONOVEN
Monitor Overrun interrupt Enable.
17
18
ENUM
DISABLED
Disabled. The MonOv interrupt is
disabled.
0
ENABLED
Enabled. The MonOv interrupt is
enabled.
1
MONRDYEN
Monitor data Ready interrupt Enable.
16
17
ENUM
DISABLED
Disabled. The MonRdy interrupt is
disabled.
0
ENABLED
Enabled. The MonRdy interrupt is
enabled.
1
MSTARBLOSSEN
Master Arbitration Loss interrupt Enable.
4
5
ENUM
DISABLED
Disabled. The MstArbLoss interrupt is
disabled.
0
ENABLED
Enabled. The MstArbLoss interrupt is
enabled.
1
MSTPENDINGEN
Master Pending interrupt Enable.
0
1
ENUM
DISABLED
Disabled. The MstPending interrupt is
disabled.
0
ENABLED
Enabled. The MstPending interrupt is
enabled.
1
MSTSTSTPERREN
Master Start/Stop Error interrupt Enable.
6
7
ENUM
DISABLED
Disabled. The MstStStpErr interrupt is
disabled.
0
ENABLED
Enabled. The MstStStpErr interrupt is
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUTEN
SCL time-out interrupt Enable.
25
26
ENUM
DISABLED
Disabled. The SCL time-out interrupt is
disabled.
0
ENABLED
Enabled. The SCL time-out interrupt is
enabled.
1
SLVDESELEN
Slave Deselect interrupt Enable.
15
16
ENUM
DISABLED
Disabled. The SlvDeSel interrupt is
disabled.
0
ENABLED
Enabled. The SlvDeSel interrupt is
enabled.
1
SLVNOTSTREN
Slave Not Stretching interrupt Enable.
11
12
ENUM
DISABLED
Disabled. The SlvNotStr interrupt is
disabled.
0
ENABLED
Enabled. The SlvNotStr interrupt is
enabled.
1
SLVPENDINGEN
Slave Pending interrupt Enable.
8
9
ENUM
DISABLED
Disabled. The SlvPending interrupt is
disabled.
0
ENABLED
Enabled. The SlvPending interrupt is
enabled.
1
INTSTAT
Interrupt Status register for Master, Slave, and Monitor functions.
0x18
read-only
n
0x0
0x0
EVENTTIMEOUT
Event time-out Interrupt flag.
24
25
MONIDLE
Monitor Idle flag.
19
20
MONOV
Monitor Overflow flag.
17
18
MONRDY
Monitor Ready.
16
17
MSTARBLOSS
Master Arbitration Loss flag.
4
5
MSTPENDING
Master Pending.
0
1
MSTSTSTPERR
Master Start/Stop Error flag.
6
7
RESERVED
Reserved.
1
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUT
SCL time-out Interrupt flag.
25
26
SLVDESEL
Slave Deselected flag.
15
16
SLVNOTSTR
Slave Not Stretching status.
11
12
SLVPENDING
Slave Pending.
8
9
MONRXDAT
Monitor receiver data register.
0x80
read-only
n
0x0
0x0
MONNACK
Monitor Received NACK.
10
11
ENUM
ACKNOWLEDGED
Acknowledged. The data currently being provided by
the monitor function was acknowledged by at least one master
or slave receiver.
0
NOT_ACKNOWLEDGED
Not acknowledged. The data currently being provided
by the monitor function was not acknowledged by any
receiver.
1
MONRESTART
Monitor Received Repeated Start.
9
10
ENUM
NO_REPEATED_START_DE
No repeated start detected. The monitor function
has not detected a Repeated Start event on the I2C
bus.
0
REPEATED_START_DETEC
Repeated start detected. The monitor function has
detected a Repeated Start event on the I2C
bus.
1
MONRXDAT
Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
0
8
MONSTART
Monitor Received Start.
8
9
ENUM
NO_START_DETECTED
No start detected. The monitor function has not
detected a Start event on the I2C bus.
0
START_DETECTED
Start detected. The monitor function has detected a
Start event on the I2C bus.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
11
32
MSTCTL
Master control register.
0x20
read-write
n
0x0
0x0
MSTCONTINUE
Master Continue. This bit is write-only.
0
1
ENUM
NO_EFFECT
No effect.
0
CONTINUE
Continue. Informs the Master function to continue
to the next operation. This must done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.
1
MSTDMA
Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.
3
4
ENUM
DISABLE
Disable. No DMA requests are generated for master
operation.
0
ENABLE
Enable. A DMA request is generated for I2C master
data operations. When this I2C master is generating
Acknowledge bits in Master Receiver mode, the acknowledge is
generated automatically.
1
MSTSTART
Master Start control. This bit is write-only.
1
2
ENUM
NO_EFFECT
No effect.
0
START
Start. A Start will be generated on the I2C bus at
the next allowed time.
1
MSTSTOP
Master Stop control. This bit is write-only.
2
3
ENUM
NO_EFFECT
No effect.
0
STOP
Stop. A Stop will be generated on the I2C bus at
the next allowed time, preceded by a NACK to the slave if
the master is receiving data from the slave (Master Receiver
mode).
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
MSTDAT
Combined Master receiver and transmitter data register.
0x28
read-write
n
0x0
0x0
DATA
Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
MSTTIME
Master timing configuration.
0x24
read-write
n
0x0
0x0
MSTSCLHIGH
Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
4
7
ENUM
2_CLOCKS
2 clocks. Minimum SCL high time is 2 clock of the
I2C clock pre-divider.
0x0
3_CLOCKS
3 clocks. Minimum SCL high time is 3 clocks of the
I2C clock pre-divider .
0x1
4_CLOCKS
4 clocks. Minimum SCL high time is 4 clock of the
I2C clock pre-divider.
0x2
5_CLOCKS
5 clocks. Minimum SCL high time is 5 clock of the
I2C clock pre-divider.
0x3
6_CLOCKS
6 clocks. Minimum SCL high time is 6 clock of the
I2C clock pre-divider.
0x4
7_CLOCKS
7 clocks. Minimum SCL high time is 7 clock of the
I2C clock pre-divider.
0x5
8_CLOCKS
8 clocks. Minimum SCL high time is 8 clock of the
I2C clock pre-divider.
0x6
9_CLOCKS
9 clocks. Minimum SCL high time is 9 clocks of the
I2C clock pre-divider.
0x7
MSTSCLLOW
Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus specification parameters tBUF and t SU;STA have the same values and are also controlled by MSTSCLLOW.
0
3
ENUM
2_CLOCKS
2 clocks. Minimum SCL low time is 2 clocks of the
I2C clock pre-divider.
0x0
3_CLOCKS
3 clocks. Minimum SCL low time is 3 clocks of the
I2C clock pre-divider.
0x1
4_CLOCKS
4 clocks. Minimum SCL low time is 4 clocks of the
I2C clock pre-divider.
0x2
5_CLOCKS
5 clocks. Minimum SCL low time is 5 clocks of the
I2C clock pre-divider.
0x3
6_CLOCKS
6 clocks. Minimum SCL low time is 6 clocks of the
I2C clock pre-divider.
0x4
7_CLOCKS
7 clocks. Minimum SCL low time is 7 clocks of the
I2C clock pre-divider.
0x5
8_CLOCKS
8 clocks. Minimum SCL low time is 8 clocks of the
I2C clock pre-divider.
0x6
9_CLOCKS
9 clocks. Minimum SCL low time is 9 clocks of the
I2C clock pre-divider.
0x7
RESERVED
Reserved.
3
4
RESERVED
Reserved.
3
4
SLVADR0
Slave address 0.
0x90
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR1
Slave address 0.
0xDC
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR2
Slave address 0.
0x12C
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVADR3
Slave address 0.
0x180
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SADISABLE
Slave Address n Disable.
0
1
ENUM
ENABLED
Enabled. Slave Address n is enabled.
0
IGNORED_SLAVE_ADDRES
Ignored Slave Address n is ignored.
1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
8
SLVCTL
Slave control register.
0x40
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
SLVCONTINUE
Slave Continue.
0
1
ENUM
NO_EFFECT
No effect.
0
CONTINUE
Continue. Informs the Slave function to continue to
the next operation. This must be done after writing transmit
data, reading received data, or any other housekeeping
related to the next bus operation.
1
SLVDMA
Slave DMA enable.
3
4
ENUM
DISABLED
Disabled. No DMA requests are issued for Slave mode
operation.
0
ENABLED
Enabled. DMA requests are issued for I2C slave data
transmission and reception.
1
SLVNACK
Slave NACK.
1
2
ENUM
NO_EFFECT
No effect.
0
NACK
NACK. Causes the Slave function to NACK the master
when the slave is receiving data from the master (Slave
Receiver mode).
1
SLVDAT
Combined Slave receiver and transmitter data register.
0x44
read-write
n
0x0
0x0
DATA
Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SLVQUAL0
Slave Qualification for address 0.
0x58
read-write
n
0x0
0x0
QUALMODE0
Qualify mode for slave address 0.
0
1
ENUM
MASK
Mask. The SLVQUAL0 field is used as a logical mask
for matching address 0.
0
EXTEND
Extend. The SLVQUAL0 field is used to extend
address 0 matching in a range of addresses.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SLVQUAL0
Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
1
8
STAT
Status register for Master, Slave, and Monitor functions.
0x4
read-write
n
0x0
0x0
EVENTTIMEOUT
Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.
24
25
ENUM
NO_TIME_OUT
No time-out. I2C bus events have not caused a
time-out.
0
EVENT_TIME_OUT
Event time-out. The time between I2C bus events has
been longer than the time specified by the I2C TIMEOUT
register.
1
MONACTIVE
Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.
18
19
ENUM
INACTIVE
Inactive. The Monitor function considers the I2C
bus to be inactive.
0
ACTIVE
Active. The Monitor function considers the I2C bus
to be active.
1
MONIDLE
Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.
19
20
ENUM
NOT_IDLE
Not idle. The I2C bus is not idle, or this flag has
been cleared by software.
0
IDLE
Idle. The I2C bus has gone idle at least once since
the last time this flag was cleared by
software.
1
MONOV
Monitor Overflow flag.
17
18
ENUM
NO_OVERRUN
No overrun. Monitor data has not
overrun.
0
OVERRUN
Overrun. A Monitor data overrun has occurred. This
can only happen when Monitor clock stretching not enabled
via the MONCLKSTR bit in the CFG register. Writing 1 to this
bit clears the flag.
1
MONRDY
Monitor Ready. This flag is cleared when the MONRXDAT register is read.
16
17
ENUM
NO_DATA
No data. The Monitor function does not currently
have data available.
0
DATA_WAITING
Data waiting. The Monitor function has data waiting
to be read.
1
MSTARBLOSS
Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
4
5
ENUM
NO_ARBITRATION_LOSS
No Arbitration Loss has occurred.
0
ARBITRATION_LOSS
Arbitration loss. The Master function has
experienced an Arbitration Loss. At this point, the Master
function has already stopped driving the bus and gone to an
idle state. Software can respond by doing nothing, or by
sending a Start in order to attempt to gain control of the
bus when it next becomes idle.
1
MSTPENDING
Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.
0
1
ENUM
IN_PROGRESS
In progress. Communication is in progress and the
Master function is busy and cannot currently accept a
command.
0
PENDING
Pending. The Master function needs software service
or is in the idle state. If the master is not in the idle
state, it is waiting to receive or transmit data or the NACK
bit.
1
MSTSTATE
Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 346 for details of state values and appropriate responses.
1
4
ENUM
IDLE
Idle. The Master function is available to be used
for a new transaction.
0x0
RECEIVE_READY
Receive ready. Received data available (Master
Receiver mode). Address plus Read was previously sent and
Acknowledged by slave.
0x1
TRANSMIT_READY
Transmit ready. Data can be transmitted (Master
Transmitter mode). Address plus Write was previously sent
and Acknowledged by slave.
0x2
NACK_ADDRESS
NACK Address. Slave NACKed address.
0x3
NACK_DATA
NACK Data. Slave NACKed transmitted
data.
0x4
MSTSTSTPERR
Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
6
7
ENUM
NO_STARTSTOP_ERROR
No Start/Stop Error has occurred.
0
THE_MASTER_FUNCTION
The Master function has experienced a Start/Stop
Error. A Start or Stop was detected at a time when it is not
allowed by the I2C specification. The Master interface has
stopped driving the bus and gone to an idle state, no action
is required. A request for a Start could be made, or
software could attempt to insure that the bus has not
stalled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
20
24
SCLTIMEOUT
SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
25
26
ENUM
NO_TIME_OUT
No time-out. SCL low time has not caused a
time-out.
0
TIME_OUT
Time-out. SCL low time has caused a
time-out.
1
SLVDESEL
Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.
15
16
ENUM
NOT_DESELECTED
Not deselected. The Slave function has not become
deselected. This does not mean that it is currently
selected. That information can be found in the SLVSEL
flag.
0
DESELECTED
Deselected. The Slave function has become
deselected. This is specifically caused by the SLVSEL flag
changing from 1 to 0. See the description of SLVSEL for
details on when that event occurs.
1
SLVIDX
Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.
12
14
ENUM
ADDRESS_0
Address 0. Slave address 0 was
matched.
0x0
ADDRESS_1
Address 1. Slave address 1 was
matched.
0x1
ADDRESS_2
Address 2. Slave address 2 was
matched.
0x2
ADDRESS_3
Address 3. Slave address 3 was
matched.
0x3
SLVNOTSTR
Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.
11
12
ENUM
STRETCHING
Stretching. The slave function is currently
stretching the I2C bus clock. Deep-Sleep or Power-down mode
cannot be entered at this time.
0
NOT_STRETCHING
Not stretching. The slave function is not currently
stretching the I 2C bus clock. Deep-sleep or Power-down mode
could be entered at this time.
1
SLVPENDING
Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register. The point in time when SlvPending is set depends on whether the I2C block is in HSCAPABLE mode. See Section 23.7.1.2.2. When the I2C block is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.
8
9
ENUM
IN_PROGRESS
In progress. The Slave function does not currently
need service.
0
PENDING
Pending. The Slave function needs service.
Information on what is needed can be found in the adjacent
SLVSTATE field.
1
SLVSEL
Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software NACKs data.
14
15
ENUM
NOT_SELECTED
Not selected. The Slave function is not currently
selected.
0
SELECTED
Selected. The Slave function is currently
selected.
1
SLVSTATE
Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 347 for state values and actions.
9
11
ENUM
SLAVE_ADDRESS
Slave address. Address plus R/W received. At least
one of the four slave addresses has been matched by
hardware.
0x0
SLAVE_RECEIVE
Slave receive. Received data is available (Slave
Receiver mode).
0x1
SLAVE_TRANSMIT
Slave transmit. Data can be transmitted (Slave
Transmitter mode).
0x2
TIMEOUT
Time-out value register.
0x10
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
TO
Time-out time value. Specifies the time-out interval value in increments of 16 I2C function clocks, as defined by the CLKDIV register. To change this value while I 2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. ... 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.
4
16
TOMIN
Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
0
4
INPUTMUX
Input multiplexing
INPUTMUX
0x0
0x0
0x1000
registers
n
DMA_ITRIG_INMUX0
Trigger select register for DMA channel 0
0x1C0
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX1
Trigger select register for DMA channel 0
0x2A4
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX10
Trigger select register for DMA channel 0
0xB5C
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX11
Trigger select register for DMA channel 0
0xC68
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX12
Trigger select register for DMA channel 0
0xD78
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX13
Trigger select register for DMA channel 0
0xE8C
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX14
Trigger select register for DMA channel 0
0xFA4
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX15
Trigger select register for DMA channel 0
0x10C0
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX16
Trigger select register for DMA channel 0
0x11E0
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX17
Trigger select register for DMA channel 0
0x1304
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX18
Trigger select register for DMA channel 0
0x142C
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX19
Trigger select register for DMA channel 0
0x1558
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX2
Trigger select register for DMA channel 0
0x38C
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX20
Trigger select register for DMA channel 0
0x1688
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX21
Trigger select register for DMA channel 0
0x17BC
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX3
Trigger select register for DMA channel 0
0x478
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX4
Trigger select register for DMA channel 0
0x568
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX5
Trigger select register for DMA channel 0
0x65C
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX6
Trigger select register for DMA channel 0
0x754
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX7
Trigger select register for DMA channel 0
0x850
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX8
Trigger select register for DMA channel 0
0x950
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_ITRIG_INMUX9
Trigger select register for DMA channel 0
0xA54
read-write
n
0x0
0x0
INP
Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer 0 Match 0 5 = Timer 0 Match 1 6 = Timer 1 Match 0 7 = Timer 2 Match 0 8 = Timer 2 Match 1 9 = Timer 3 Match 0 10 = Timer 4 Match 0 11 = Timer 4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3
0
5
RESERVED
Reserved.
5
32
DMA_OTRIG_INMUX0
DMA output trigger selection to become DMA trigger 16
0x280
read-write
n
0x0
0x0
INP
DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).
0
5
RESERVED
Reserved.
5
32
DMA_OTRIG_INMUX1
DMA output trigger selection to become DMA trigger 16
0x3C4
read-write
n
0x0
0x0
INP
DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).
0
5
RESERVED
Reserved.
5
32
DMA_OTRIG_INMUX2
DMA output trigger selection to become DMA trigger 16
0x50C
read-write
n
0x0
0x0
INP
DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).
0
5
RESERVED
Reserved.
5
32
DMA_OTRIG_INMUX3
DMA output trigger selection to become DMA trigger 16
0x658
read-write
n
0x0
0x0
INP
DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).
0
5
RESERVED
Reserved.
5
32
FREQMEAS_REF
Clock selection for frequency measurement function reference clock
0x160
read-write
n
0x0
0x0
CLKIN
Clock source number (decimal value) for frequency measure function target clock: 0 = System oscillator (MAIN_OSC) 1 = IRC oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.21) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
0
5
RESERVED
Reserved.
5
32
FREQMEAS_TARGET
Clock selection for frequency measurement function target clock
0x164
read-write
n
0x0
0x0
CLKIN
Clock source number (decimal value) for frequency measure function target clock: 0 = System oscillator (MAIN_OSC) 1 = IRC oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.18) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
0
5
RESERVED
Reserved.
5
32
PINTSEL0
Pin interrupt select register 0
0x180
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
RESERVED
Reserved
8
32
PINTSEL1
Pin interrupt select register 0
0x244
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
RESERVED
Reserved
8
32
PINTSEL2
Pin interrupt select register 0
0x30C
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
RESERVED
Reserved
8
32
PINTSEL3
Pin interrupt select register 0
0x3D8
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
RESERVED
Reserved
8
32
PINTSEL4
Pin interrupt select register 0
0x4A8
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
RESERVED
Reserved
8
32
PINTSEL5
Pin interrupt select register 0
0x57C
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
RESERVED
Reserved
8
32
PINTSEL6
Pin interrupt select register 0
0x654
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
RESERVED
Reserved
8
32
PINTSEL7
Pin interrupt select register 0
0x730
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).
0
8
RESERVED
Reserved
8
32
IOCON
I/O pin configuration
IOCON
0x0
0x0
0x1000
registers
n
PIO0_0
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x0
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_1
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x4
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_10
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0xDC
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_11
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x108
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_12
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x138
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_13
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x16C
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_14
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x1A4
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_15
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x1E0
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_16
Digital I/O control for port 0 pins PIO0_16 to PIO0_17.
0x80
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_17
Digital I/O control for port 0 pins PIO0_16 to PIO0_17.
0xC4
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_18
Digital I/O control for port 0 pins PIO0_18 to PIO0_22.
0x90
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_19
Digital I/O control for port 0 pins PIO0_18 to PIO0_22.
0xDC
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_2
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0xC
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_20
Digital I/O control for port 0 pins PIO0_18 to PIO0_22.
0x12C
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_21
Digital I/O control for port 0 pins PIO0_18 to PIO0_22.
0x180
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_22
Digital I/O control for port 0 pins PIO0_18 to PIO0_22.
0x1D8
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_23
Digital I/O control for port 0 pins PIO0_23 to PIO0_28. These pins support I2C with true open-drain, drive and filtering for modes up to Fast-mode Plus.
0xB8
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
I2CDRIVE
Controls the current sink capability of the pin.
9
10
ENUM
LOW_DRIVE
Low drive. Output drive sink is 4 mA. This is
sufficient for standard and fast mode I2C.
0
HIGH_DRIVE
High drive. Output drive sink is 20 mA. This is
needed for Fast Mode Plus I 2C. Refer to the appropriate
specific device data sheet for details.
1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
11
ENUM
ENABLED
Enabled. I2C 50 ns glitch filter
enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter
disabled.
1
I2CSLEW
Controls slew rate of I2C pad.
5
6
ENUM
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
1
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
PIO0_24
Digital I/O control for port 0 pins PIO0_23 to PIO0_28. These pins support I2C with true open-drain, drive and filtering for modes up to Fast-mode Plus.
0x118
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
I2CDRIVE
Controls the current sink capability of the pin.
9
10
ENUM
LOW_DRIVE
Low drive. Output drive sink is 4 mA. This is
sufficient for standard and fast mode I2C.
0
HIGH_DRIVE
High drive. Output drive sink is 20 mA. This is
needed for Fast Mode Plus I 2C. Refer to the appropriate
specific device data sheet for details.
1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
11
ENUM
ENABLED
Enabled. I2C 50 ns glitch filter
enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter
disabled.
1
I2CSLEW
Controls slew rate of I2C pad.
5
6
ENUM
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
1
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
PIO0_25
Digital I/O control for port 0 pins PIO0_23 to PIO0_28. These pins support I2C with true open-drain, drive and filtering for modes up to Fast-mode Plus.
0x17C
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
I2CDRIVE
Controls the current sink capability of the pin.
9
10
ENUM
LOW_DRIVE
Low drive. Output drive sink is 4 mA. This is
sufficient for standard and fast mode I2C.
0
HIGH_DRIVE
High drive. Output drive sink is 20 mA. This is
needed for Fast Mode Plus I 2C. Refer to the appropriate
specific device data sheet for details.
1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
11
ENUM
ENABLED
Enabled. I2C 50 ns glitch filter
enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter
disabled.
1
I2CSLEW
Controls slew rate of I2C pad.
5
6
ENUM
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
1
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
PIO0_26
Digital I/O control for port 0 pins PIO0_23 to PIO0_28. These pins support I2C with true open-drain, drive and filtering for modes up to Fast-mode Plus.
0x1E4
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
I2CDRIVE
Controls the current sink capability of the pin.
9
10
ENUM
LOW_DRIVE
Low drive. Output drive sink is 4 mA. This is
sufficient for standard and fast mode I2C.
0
HIGH_DRIVE
High drive. Output drive sink is 20 mA. This is
needed for Fast Mode Plus I 2C. Refer to the appropriate
specific device data sheet for details.
1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
11
ENUM
ENABLED
Enabled. I2C 50 ns glitch filter
enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter
disabled.
1
I2CSLEW
Controls slew rate of I2C pad.
5
6
ENUM
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
1
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
PIO0_27
Digital I/O control for port 0 pins PIO0_23 to PIO0_28. These pins support I2C with true open-drain, drive and filtering for modes up to Fast-mode Plus.
0x250
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
I2CDRIVE
Controls the current sink capability of the pin.
9
10
ENUM
LOW_DRIVE
Low drive. Output drive sink is 4 mA. This is
sufficient for standard and fast mode I2C.
0
HIGH_DRIVE
High drive. Output drive sink is 20 mA. This is
needed for Fast Mode Plus I 2C. Refer to the appropriate
specific device data sheet for details.
1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
11
ENUM
ENABLED
Enabled. I2C 50 ns glitch filter
enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter
disabled.
1
I2CSLEW
Controls slew rate of I2C pad.
5
6
ENUM
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
1
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
PIO0_28
Digital I/O control for port 0 pins PIO0_23 to PIO0_28. These pins support I2C with true open-drain, drive and filtering for modes up to Fast-mode Plus.
0x2C0
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
I2CDRIVE
Controls the current sink capability of the pin.
9
10
ENUM
LOW_DRIVE
Low drive. Output drive sink is 4 mA. This is
sufficient for standard and fast mode I2C.
0
HIGH_DRIVE
High drive. Output drive sink is 20 mA. This is
needed for Fast Mode Plus I 2C. Refer to the appropriate
specific device data sheet for details.
1
I2CFILTER
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
10
11
ENUM
ENABLED
Enabled. I2C 50 ns glitch filter
enabled.
0
DISABLED
Disabled. I2C 50 ns glitch filter
disabled.
1
I2CSLEW
Controls slew rate of I2C pad.
5
6
ENUM
I2C_MODE
I2C mode.
0
GPIO_MODE
GPIO mode.
1
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
5
PIO0_29
Digital I/O control for port 0 pins PIO0_29 to PIO0_31. These pins include an ADC input.
0xE8
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO0_3
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x18
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_30
Digital I/O control for port 0 pins PIO0_29 to PIO0_31. These pins include an ADC input.
0x160
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO0_31
Digital I/O control for port 0 pins PIO0_29 to PIO0_31. These pins include an ADC input.
0x1DC
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO0_4
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x28
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_5
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x3C
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_6
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x54
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_7
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x70
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_8
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0x90
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO0_9
Digital I/O control for port 0 pins PIO0_0 to PIO0_15.
0xB4
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_0
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x100
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_1
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x184
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_10
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x1F0
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_11
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x29C
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_12
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x34C
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_13
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x400
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_14
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x4B8
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_15
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x574
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_16
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x634
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_17
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x6F8
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
PIO1_2
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x20C
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_3
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x298
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_4
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x328
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_5
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x3BC
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_6
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x454
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_7
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x4F0
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_8
Digital I/O control for port 1 pins PIO0_0 to PIO0_8. These pins include an ADC input.
0x590
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
PIO1_9
Digital I/O control for port 1 pins PIO1_9 to PIO1_17.
0x148
read-write
n
0x0
0x0
DIGIMODE
Select Analog/Digital mode.
7
8
ENUM
ANALOG_MODE
Analog mode.
0
DIGITAL_MODE
Digital mode.
1
FILTEROFF
Controls input glitch filter.
8
9
ENUM
FILTER_ENABLED
Filter enabled. Noise pulses below approximately 10
ns are filtered out
0
FILTER_DISABLED
Filter disabled. No input filtering is
done
1
FUNC
Selects pin function.
0
3
INVERT
Input polarity.
6
7
ENUM
DISABLED
Disabled. Input function is not
inverted.
0
ENABLED
Enabled. Input is function inverted.
1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
5
ENUM
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor
enabled).
0x0
PULL_DOWN
Pull-down. Pull-down resistor
enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Controls open-drain mode.
10
11
ENUM
NORMAL
Normal. Normal push-pull output
0
OPEN_DRAIN
Open-drain. Simulated open-drain output (high drive
disabled)
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
6
SLEW
Driver slew rate.
9
10
ENUM
STANDARD_MODE
Standard mode, output slew rate control is enabled.
More outputs can be switched simultaneously.
0
FAST_MODE
Fast mode, slew rate control is disabled. Refer to
the appropriate specific device data sheet for
details.
1
MAILBOX
Mailbox
MAILBOX
0x0
0x0
0x1000
registers
n
MAILBOX
31
IRQ0
Interrupt request register for the Cortex-M0+ CPU.
0x0
read-write
n
0x0
0x0
INTREQ
If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller.
0
32
IRQ0CLR
Clear bits in IRQ0
0x8
write-only
n
0x0
0x0
INTREQCLR
Writing 1 clears the corresponding bit in the IRQ0 register.
0
32
IRQ0SET
Set bits in IRQ0
0x4
write-only
n
0x0
0x0
INTREQSET
Writing 1 sets the corresponding bit in the IRQ0 register.
0
32
IRQ1
Interrupt request register for the Cortex M4 CPU.
0x10
read-write
n
0x0
0x0
INTREQ
If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller.
0
32
IRQ1CLR
Clear bits in IRQ1
0x18
write-only
n
0x0
0x0
INTREQCLR
Writing 1 clears the corresponding bit in the IRQ1 register.
0
32
IRQ1SET
Set bits in IRQ1
0x14
write-only
n
0x0
0x0
INTREQSET
Writing 1 sets the corresponding bit in the IRQ1 register.
0
32
MUTEX
Mutual exclusion register
0xF8
read-write
n
0x0
0x0
EX
Cleared when read, set when written. See usage description above.
0
1
RESERVED
Reserved
1
32
MRT
Multi-Rate Timer
MRT
0x0
0x0
0x1000
registers
n
MRT
10
CTRL0
MRTn Control register. This register controls the MRTn modes.
0x10
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
ENUM
DISABLED
TIMERn interrupt is disabled.
0
ENABLED
TIMERn interrupt is enabled.
1
MODE
Selects timer mode.
1
3
ENUM
REPEAT_INTERRUPT_MOD
Repeat interrupt mode.
0x0
ONE_SHOT_INTERRUPT_M
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
RESERVED
Reserved.
0x3
RESERVED
Reserved.
3
32
CTRL1
MRTn Control register. This register controls the MRTn modes.
0x28
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
ENUM
DISABLED
TIMERn interrupt is disabled.
0
ENABLED
TIMERn interrupt is enabled.
1
MODE
Selects timer mode.
1
3
ENUM
REPEAT_INTERRUPT_MOD
Repeat interrupt mode.
0x0
ONE_SHOT_INTERRUPT_M
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
RESERVED
Reserved.
0x3
RESERVED
Reserved.
3
32
CTRL2
MRTn Control register. This register controls the MRTn modes.
0x50
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
ENUM
DISABLED
TIMERn interrupt is disabled.
0
ENABLED
TIMERn interrupt is enabled.
1
MODE
Selects timer mode.
1
3
ENUM
REPEAT_INTERRUPT_MOD
Repeat interrupt mode.
0x0
ONE_SHOT_INTERRUPT_M
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
RESERVED
Reserved.
0x3
RESERVED
Reserved.
3
32
CTRL3
MRTn Control register. This register controls the MRTn modes.
0x88
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
ENUM
DISABLED
TIMERn interrupt is disabled.
0
ENABLED
TIMERn interrupt is enabled.
1
MODE
Selects timer mode.
1
3
ENUM
REPEAT_INTERRUPT_MOD
Repeat interrupt mode.
0x0
ONE_SHOT_INTERRUPT_M
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
RESERVED
Reserved.
0x3
RESERVED
Reserved.
3
32
IDLE_CH
Idle channel register. This register returns the number of the first idle channel.
0xF4
read-only
n
0x0
0x0
CHAN
Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.
4
8
RESERVED
Reserved.
0
4
RESERVED
Reserved.
0
4
INTVAL0
MRTn Time interval value register. This value is loaded into the TIMER0 register.
0x0
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
24
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
32
ENUM
NO_FORCE_LOAD
No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
31
INTVAL1
MRTn Time interval value register. This value is loaded into the TIMER0 register.
0x10
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
24
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
32
ENUM
NO_FORCE_LOAD
No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
31
INTVAL2
MRTn Time interval value register. This value is loaded into the TIMER0 register.
0x30
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
24
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
32
ENUM
NO_FORCE_LOAD
No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
31
INTVAL3
MRTn Time interval value register. This value is loaded into the TIMER0 register.
0x60
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
24
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
32
ENUM
NO_FORCE_LOAD
No force load. The load from the INTVALn register
to the TIMERn register is processed at the end of the time
interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is
immediately loaded into the TIMERn register while TIMERn is
running.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
31
IRQ_FLAG
Global interrupt flag register
0xF8
read-write
n
0x0
0x0
GFLAG0
Monitors the interrupt flag of TIMER0.
0
1
ENUM
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMER0 has reached the end of the time interval. If the
INTEN bit in the CONTROL0 register is also set to 1, the
interrupt for timer channel 0 and the global interrupt are
raised. Writing a 1 to this bit clears the interrupt
request.
1
GFLAG1
Monitors the interrupt flag of TIMER1. See description of channel 0.
1
2
GFLAG2
Monitors the interrupt flag of TIMER2. See description of channel 0.
2
3
GFLAG3
Monitors the interrupt flag of TIMER3. See description of channel 0.
3
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
MODCFG
Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature.
0xF0
read-write
n
0x0
0x0
MULTITASK
Selects the operating mode for the INUSE flags and the IDLE_CH register. See Idle channel register (IDLE_CH) for details.
31
32
ENUM
HARDWARE_STATUS_MODE
Hardware status mode. In this mode, the INUSE(n)
flags for all channels are reset.
0
MULTI_TASK_MODE
Multi-task mode.
1
NOB
Identifies the number of timer bits in this MRT.
4
9
NOC
Identifies the number of channels in this MRT.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
31
STAT0
MRTn Status register.
0x18
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
ENUM
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.
1
INUSE
Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH.
2
3
ENUM
NO
This channel is not in use.
0
YES
This channel is in use.
1
RESERVED
Reserved.
2
32
RUN
Indicates the state of TIMERn. This bit is read-only.
1
2
ENUM
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
1
STAT1
MRTn Status register.
0x34
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
ENUM
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.
1
INUSE
Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH.
2
3
ENUM
NO
This channel is not in use.
0
YES
This channel is in use.
1
RESERVED
Reserved.
2
32
RUN
Indicates the state of TIMERn. This bit is read-only.
1
2
ENUM
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
1
STAT2
MRTn Status register.
0x60
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
ENUM
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.
1
INUSE
Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH.
2
3
ENUM
NO
This channel is not in use.
0
YES
This channel is in use.
1
RESERVED
Reserved.
2
32
RUN
Indicates the state of TIMERn. This bit is read-only.
1
2
ENUM
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
1
STAT3
MRTn Status register.
0x9C
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
ENUM
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent
to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because
TIMERn has reached the end of the time interval. If the
INTEN bit in the CONTROLn is also set to 1, the interrupt
for timer channel n and the global interrupt are raised.
Writing a 1 to this bit clears the interrupt
request.
1
INUSE
Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH.
2
3
ENUM
NO
This channel is not in use.
0
YES
This channel is in use.
1
RESERVED
Reserved.
2
32
RUN
Indicates the state of TIMERn. This bit is read-only.
1
2
ENUM
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
1
TIMER0
MRTn Timer register. This register reads the value of the down-counter.
0x8
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
32
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
24
TIMER1
MRTn Timer register. This register reads the value of the down-counter.
0x1C
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
32
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
24
TIMER2
MRTn Timer register. This register reads the value of the down-counter.
0x40
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
32
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
24
TIMER3
MRTn Timer register. This register reads the value of the down-counter.
0x74
read-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
32
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
24
PINT
Pin interrupt and pattern match engine
PINT
0x0
0x0
0x1000
registers
n
PIN_INT0
5
PIN_INT1
6
PIN_INT2
7
PIN_INT3
8
PIN_INT4
33
PIN_INT5
34
PIN_INT6
35
PIN_INT7
36
CIENF
Pin interrupt active level or falling edge interrupt clear register
0x18
write-only
n
0x0
0x0
CENAF
Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.
0
8
RESERVED
Reserved.
8
32
CIENR
Pin interrupt level (rising edge interrupt) clear register
0xC
write-only
n
0x0
0x0
CENRL
Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.
0
8
RESERVED
Reserved.
8
32
FALL
Pin interrupt falling edge register
0x20
read-write
n
0x0
0x0
FDET
Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.
0
8
RESERVED
Reserved.
8
32
IENF
Pin interrupt active level or falling edge interrupt enable register
0x10
read-write
n
0x0
0x0
ENAF
Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.
0
8
RESERVED
Reserved.
8
32
IENR
Pin interrupt level or rising edge interrupt enable register
0x4
read-write
n
0x0
0x0
ENRL
Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written..
8
32
ISEL
Pin Interrupt Mode register
0x0
read-write
n
0x0
0x0
PMODE
Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
IST
Pin interrupt status register
0x24
read-write
n
0x0
0x0
PSTAT
Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
0
8
RESERVED
Reserved.
8
32
PMCFG
Pattern match interrupt bit slice configuration register
0x30
read-write
n
0x0
0x0
CFG0
Specifies the match contribution condition for bit slice 0.
8
11
ENUM
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to
a product term match.
0x0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x2
STICKY_RISING_OR_FAL
Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level
on the specified input.
0x5
CONSTANT_0
Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.
0x7
CFG1
Specifies the match contribution condition for bit slice 1.
11
14
ENUM
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to
a product term match.
0x0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x2
STICKY_RISING_OR_FAL
Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level
on the specified input.
0x5
CONSTANT_0
Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.
0x7
CFG2
Specifies the match contribution condition for bit slice 2.
14
17
ENUM
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to
a product term match.
0x0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x2
STICKY_RISING_OR_FAL
Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level
on the specified input.
0x5
CONSTANT_0
Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.
0x7
CFG3
Specifies the match contribution condition for bit slice 3.
17
20
ENUM
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to
a product term match.
0x0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x2
STICKY_RISING_OR_FAL
Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level
on the specified input.
0x5
CONSTANT_0
Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.
0x7
CFG4
Specifies the match contribution condition for bit slice 4.
20
23
ENUM
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to
a product term match.
0x0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x2
STICKY_RISING_OR_FAL
Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level
on the specified input.
0x5
CONSTANT_0
Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.
0x7
CFG5
Specifies the match contribution condition for bit slice 5.
23
26
ENUM
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to
a product term match.
0x0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x2
STICKY_RISING_OR_FAL
Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level
on the specified input.
0x5
CONSTANT_0
Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.
0x7
CFG6
Specifies the match contribution condition for bit slice 6.
26
29
ENUM
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to
a product term match.
0x0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x2
STICKY_RISING_OR_FAL
Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level
on the specified input.
0x5
CONSTANT_0
Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.
0x7
CFG7
Specifies the match contribution condition for bit slice 7.
29
32
ENUM
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to
a product term match.
0x0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge
on the specified input has occurred since the last time the
edge detection for this bit slice was cleared. This bit is
only cleared when the PMCFG or the PMSRC registers are
written to.
0x2
STICKY_RISING_OR_FAL
Sticky rising or falling edge. Match occurs if
either a rising or falling edge on the specified input has
occurred since the last time the edge detection for this bit
slice was cleared. This bit is only cleared when the PMCFG
or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when
there is a high level on the input specified for this bit
slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level
on the specified input.
0x5
CONSTANT_0
Constant 0. This bit slice never contributes to a
match (should be used to disable any unused bit
slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match
occurs on an event - i.e. when either a rising or falling
edge is first detected on the specified input (this is a
non-sticky version of value 0x3) . This bit is cleared after
one clock cycle.
0x7
PROD_ENDPTS0
Determines whether slice 0 is an endpoint.
0
1
ENUM
NO_EFFECT
No effect. Slice 0 is not an
endpoint.
0
ENDPOINT
endpoint. Slice 0 is the endpoint of a product term
(minterm). Pin interrupt 0 in the NVIC is raised if the
minterm evaluates as true.
1
PROD_ENDPTS1
Determines whether slice 1 is an endpoint.
1
2
ENUM
NO_EFFECT
No effect. Slice 1 is not an
endpoint.
0
ENDPOINT
endpoint. Slice 1 is the endpoint of a product term
(minterm). Pin interrupt 1 in the NVIC is raised if the
minterm evaluates as true.
1
PROD_ENDPTS2
Determines whether slice 2 is an endpoint.
2
3
ENUM
NO_EFFECT
No effect. Slice 2 is not an
endpoint.
0
ENDPOINT
endpoint. Slice 2 is the endpoint of a product term
(minterm). Pin interrupt 2 in the NVIC is raised if the
minterm evaluates as true.
1
PROD_ENDPTS3
Determines whether slice 3 is an endpoint.
3
4
ENUM
NO_EFFECT
No effect. Slice 3 is not an
endpoint.
0
ENDPOINT
endpoint. Slice 3 is the endpoint of a product term
(minterm). Pin interrupt 3 in the NVIC is raised if the
minterm evaluates as true.
1
PROD_ENDPTS4
Determines whether slice 4 is an endpoint.
4
5
ENUM
NO_EFFECT
No effect. Slice 4 is not an
endpoint.
0
ENDPOINT
endpoint. Slice 4 is the endpoint of a product term
(minterm). Pin interrupt 4 in the NVIC is raised if the
minterm evaluates as true.
1
PROD_ENDPTS5
Determines whether slice 5 is an endpoint.
5
6
ENUM
NO_EFFECT
No effect. Slice 5 is not an
endpoint.
0
ENDPOINT
endpoint. Slice 5 is the endpoint of a product term
(minterm). Pin interrupt 5 in the NVIC is raised if the
minterm evaluates as true.
1
PROD_ENDPTS6
Determines whether slice 6 is an endpoint.
6
7
ENUM
NO_EFFECT
No effect. Slice 6 is not an
endpoint.
0
ENDPOINT
endpoint. Slice 6 is the endpoint of a product term
(minterm). Pin interrupt 6 in the NVIC is raised if the
minterm evaluates as true.
1
RESERVED
Reserved. Bit slice 7 is automatically considered a product end point.
7
8
PMCTRL
Pattern match interrupt control register
0x28
read-write
n
0x0
0x0
ENA_RXEV
Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
1
2
ENUM
DISABLED
Disabled. RXEV output to the CPU is
disabled.
0
ENABLED
Enabled. RXEV output to the CPU is
enabled.
1
PMAT
This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.
24
32
RESERVED
Reserved. Do not write 1s to unused bits.
2
24
SEL_PMATCH
Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
0
1
ENUM
PIN_INTERRUPT
Pin interrupt. Interrupts are driven in response to
the standard pin interrupt function.
0
PATTERN_MATCH
Pattern match. Interrupts are driven in response to
pattern matches.
1
PMSRC
Pattern match interrupt bit-slice source register
0x2C
read-write
n
0x0
0x0
Reserved
Software should not write 1s to unused bits.
0
8
SRC0
Selects the input source for bit slice 0
8
11
ENUM
INPUT_0
Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 0.
0x0
INPUT_1
Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 0.
0x1
INPUT_2
Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 0.
0x2
INPUT_3
Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 0.
0x3
INPUT_4
Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 0.
0x4
INPUT_5
Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 0.
0x5
INPUT_6
Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 0.
0x6
INPUT_7
Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 0.
0x7
SRC1
Selects the input source for bit slice 1
11
14
ENUM
INPUT_0
Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 1.
0x0
INPUT_1
Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 1.
0x1
INPUT_2
Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 1.
0x2
INPUT_3
Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 1.
0x3
INPUT_4
Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 1.
0x4
INPUT_5
Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 1.
0x5
INPUT_6
Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 1.
0x6
INPUT_7
Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 1.
0x7
SRC2
Selects the input source for bit slice 2
14
17
ENUM
INPUT_0
Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 2.
0x0
INPUT_1
Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 2.
0x1
INPUT_2
Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 2.
0x2
INPUT_3
Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 2.
0x3
INPUT_4
Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 2.
0x4
INPUT_5
Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 2.
0x5
INPUT_6
Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 2.
0x6
INPUT_7
Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 2.
0x7
SRC3
Selects the input source for bit slice 3
17
20
ENUM
INPUT_0
Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 3.
0x0
INPUT_1
Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 3.
0x1
INPUT_2
Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 3.
0x2
INPUT_3
Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 3.
0x3
INPUT_4
Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 3.
0x4
INPUT_5
Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 3.
0x5
INPUT_6
Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 3.
0x6
INPUT_7
Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 3.
0x7
SRC4
Selects the input source for bit slice 4
20
23
ENUM
INPUT_0
Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 4.
0x0
INPUT_1
Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 4.
0x1
INPUT_2
Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 4.
0x2
INPUT_3
Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 4.
0x3
INPUT_4
Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 4.
0x4
INPUT_5
Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 4.
0x5
INPUT_6
Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 4.
0x6
INPUT_7
Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 4.
0x7
SRC5
Selects the input source for bit slice 5
23
26
ENUM
INPUT_0
Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 5.
0x0
INPUT_1
Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 5.
0x1
INPUT_2
Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 5.
0x2
INPUT_3
Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 5.
0x3
INPUT_4
Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 5.
0x4
INPUT_5
Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 5.
0x5
INPUT_6
Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 5.
0x6
INPUT_7
Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 5.
0x7
SRC6
Selects the input source for bit slice 6
26
29
ENUM
INPUT_0
Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 6.
0x0
INPUT_1
Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 6.
0x1
INPUT_2
Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 6.
0x2
INPUT_3
Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 6.
0x3
INPUT_4
Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 6.
0x4
INPUT_5
Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 6.
0x5
INPUT_6
Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 6.
0x6
INPUT_7
Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 6.
0x7
SRC7
Selects the input source for bit slice 7
29
32
ENUM
INPUT_0
Input 0. Selects the pin selected in the PINTSEL0
register as the source to bit slice 7.
0x0
INPUT_1
Input 1. Selects the pin selected in the PINTSEL1
register as the source to bit slice 7.
0x1
INPUT_2
Input 2. Selects the pin selected in the PINTSEL2
register as the source to bit slice 7.
0x2
INPUT_3
Input 3. Selects the pin selected in the PINTSEL3
register as the source to bit slice 7.
0x3
INPUT_4
Input 4. Selects the pin selected in the PINTSEL4
register as the source to bit slice 7.
0x4
INPUT_5
Input 5. Selects the pin selected in the PINTSEL5
register as the source to bit slice 7.
0x5
INPUT_6
Input 6. Selects the pin selected in the PINTSEL6
register as the source to bit slice 7.
0x6
INPUT_7
Input 7. Selects the pin selected in the PINTSEL7
register as the source to bit slice 7.
0x7
RISE
Pin interrupt rising edge register
0x1C
read-write
n
0x0
0x0
RDET
Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
0
8
RESERVED
Reserved.
8
32
SIENF
Pin interrupt active level or falling edge interrupt set register
0x14
write-only
n
0x0
0x0
RESERVED
Reserved.
8
32
SETENAF
Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.
0
8
SIENR
Pin interrupt level or rising edge interrupt set register
0x8
write-only
n
0x0
0x0
RESERVED
Reserved.
8
32
SETENRL
Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
0
8
RIT
Repetitive Interrupt Timer
RIT
0x0
0x0
0x1000
registers
n
RIT
40
COMPVAL
Compare value LSB register. Holds the 32 LSBs of the compare value.
0x0
read-write
n
0x0
0x0
RICOMP
Compare register. Holds the 32 LSBs of the value which is compared to the counter.
0
32
COMPVAL_H
Compare value MSB register. Holds the 16 MSBs of the compare value.
0x10
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RICOMP
Compare value MSB register. Holds the 16 MSBs of the value which is compared to the counter.
0
16
COUNTER
Counter LSB register. 32 LSBs of the counter.
0xC
read-write
n
0x0
0x0
RICOUNTER
32 LSBs of the up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.
0
32
COUNTER_H
Counter MSB register. 16 MSBs of the counter.
0x1C
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RICOUNTER
16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.
0
16
CTRL
Control register.
0x8
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
32
RITEN
Timer enable.
3
4
ENUM
TIMER_DISABLED
Timer disabled.
0
TIMER_ENABLED
Timer enabled. This can be overruled by a debug
halt if enabled in bit 2.
1
RITENBR
Timer enable for debug
2
3
ENUM
DEBUG
Debug has no effect on the timer
operation.
0
HALT
The timer is halted when the processor is halted
for debugging.
1
RITENCLR
Timer enable clear
1
2
ENUM
NOCLEAR
The timer will not be cleared to 0.
0
CLEAR
The timer will be cleared to 0 whenever the counter
value equals the masked compare value specified by the
contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers.
This will occur on the same clock that sets the interrupt
flag.
1
RITINT
Interrupt flag
0
1
ENUM
NOMTCH
The counter value does not equal the masked compare
value.
0
MATCH
This bit is set to 1 by hardware whenever the
counter value equals the masked compare value specified by
the contents of RICOMPVAL and RIMASK registers. Writing a 1
to this bit will clear it to 0. Writing a 0 has no
effect.
1
MASK
Mask LSB register. This register holds the 32 LSB s of the mask value. A 1 written to any bit will force the compare to be true for the corresponding bit of the counter and compare register.
0x4
read-write
n
0x0
0x0
RIMASK
Mask register. This register holds the 32 LSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).
0
32
MASK_H
Mask MSB register. This register holds the 16 MSBs of the mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.
0x14
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RIMASK
Mask register. This register holds the 16 MSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).
0
16
RTC
Real-Time Clock
RTC
0x0
0x0
0x1000
registers
n
RTC
29
COUNT
RTC counter register
0x8
read-write
n
0x0
0x0
VAL
A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set.
0
32
CTRL
RTC control register
0x0
read-write
n
0x0
0x0
ALARM1HZ
RTC 1 Hz timer alarm flag status.
2
3
ENUM
NO_MATCH
No match. No match has occurred on the 1 Hz RTC
timer. Writing a 0 has no effect.
0
MATCH
Match. A match condition has occurred on the 1 Hz
RTC timer. This flag generates an RTC alarm interrupt
request RTC_ALARM which can also wake up the part from any
low power mode. Writing a 1 clears this bit.
1
ALARMDPD_EN
RTC 1 Hz timer alarm enable for Deep power-down.
4
5
ENUM
DISABLE
Disable. A match on the 1 Hz RTC timer will not
bring the part out of Deep power-down mode.
0
ENABLE
Enable. A match on the 1 Hz RTC timer bring the
part out of Deep power-down mode.
1
OFD
Oscillator fail detect status.
1
2
ENUM
RUN
Run. The RTC oscillator is running properly.
Writing a 0 has no effect.
0
FAIL
Fail. RTC oscillator fail detected. Clear this flag
after the following power-up. Writing a 1 clears this
bit.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
RTC1KHZ_EN
RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
6
7
ENUM
DISABLE
Disable. A match on the 1 kHz RTC timer will not
bring the part out of Deep power-down mode.
0
ENABLE
Enable. The 1 kHz RTC timer is
enabled.
1
RTC_EN
RTC enable.
7
8
ENUM
DISABLE
Disable. The RTC 1 Hz and 1 kHz clocks are shut
down and the RTC operation is disabled. This bit should be 0
when writing to load a value in the RTC counter
register.
0
ENABLE
Enable. The 1 Hz RTC clock is running and RTC
operation is enabled. This bit must be set to initiate
operation of the RTC. The first clock to the RTC counter
occurs 1 s after this bit is set. To also enable the
high-resolution, 1 kHz clock, set bit 6 in this
register.
1
SWRESET
Software reset control
0
1
ENUM
NOT_IN_RESET
Not in reset. The RTC is not held in reset. This
bit must be cleared prior to configuring or initiating any
operation of the RTC.
0
IN_RESET
In reset. The RTC is held in reset. All register
bits within the RTC will be forced to their reset value
except the OFD bit. This bit must be cleared before writing
to any register in the RTC - including writes to set any of
the other bits within this register. Do not attempt to write
to any bits of this register at the same time that the reset
bit is being cleared.
1
WAKE1KHZ
RTC 1 kHz timer wake-up flag status.
3
4
ENUM
RUN
Run. The RTC 1 kHz timer is running. Writing a 0
has no effect.
0
TIME_OUT
Time-out. The 1 kHz high-resolution/wake-up timer
has timed out. This flag generates an RTC wake-up interrupt
request RTC-WAKE which can also wake up the part from any
low power mode. Writing a 1 clears this bit.
1
WAKEDPD_EN
RTC 1 kHz timer wake-up enable for Deep power-down.
5
6
ENUM
DISABLE
Disable. A match on the 1 kHz RTC timer will not
bring the part out of Deep power-down mode.
0
ENABLE
Enable. A match on the 1 kHz RTC timer bring the
part out of Deep power-down mode.
1
MATCH
RTC match register
0x4
read-write
n
0x0
0x0
MATVAL
Contains the match value against which the 1 Hz RTC timer will be compared to generate set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
0
32
WAKE
RTC high-resolution/wake-up timer control register
0xC
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written..
16
32
VAL
A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress.
0
16
SCT0
State Configurable Timer/PWM 0
SCT0
0x0
0x0
0x1000
registers
n
SCT0
16
CAP0
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0x200
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP1
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0x304
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP10
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0xCDC
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP11
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0xE08
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP12
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0xF38
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP2
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0x40C
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP3
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0x518
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP4
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0x628
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP5
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0x73C
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP6
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0x854
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP7
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0x970
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP8
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0xA90
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAP9
SCT capture register of capture channel 0 to 12; REGMOD0 to REGMODE12 = 1
MATCH%s
0xBB4
read-only
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
32
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
CAPCTRL0
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x400
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL1
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x604
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL10
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x18DC
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL11
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x1B08
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL12
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x1D38
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL2
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x80C
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL3
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0xA18
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL4
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0xC28
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL5
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0xE3C
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL6
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x1054
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL7
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x1270
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL8
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x1490
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CAPCTRL9
SCT capture control register 0 to 12; REGMOD0 = 1 to REGMODE12 = 1
MATCHREL%s
0x16B4
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
CONEN
SCT conflict enable register
0xF8
read-write
n
0x0
0x0
NCEN
The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.
0
8
RESERVED
Reserved
10
32
CONFIG
SCT configuration register
0x0
read-write
n
0x0
0x0
AUTOLIMIT_H
A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
18
19
AUTOLIMIT_L
A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
17
18
CKSEL
SCT clock select
3
7
ENUM
INPUT_0_RISING_EDGES
Input 0 rising edges.
0x0
INPUT_0_FALLING_EDGE
Input 0 falling edges.
0x1
INPUT_1_RISING_EDGES
Input 1 rising edges.
0x2
INPUT_1_FALLING_EDGE
Input 1 falling edges.
0x3
INPUT_2_RISING_EDGES
Input 2 rising edges.
0x4
INPUT_2_FALLING_EDGE
Input 2 falling edges.
0x5
INPUT_3_RISING_EDGES
Input 3 rising edges.
0x6
INPUT_3_FALLING_EDGE
Input 3 falling edges.
0x7
INPUT_4_RISING_EDGES
Input 4 rising edges.
0x8
INPUT_4_FALLING_EDGE
Input 4 falling edges.
0x9
INPUT_5_RISING_EDGES
Input 5 rising edges.
0xA
INPUT_5_FALLING_EDGE
Input 5 falling edges.
0xB
INPUT_6_RISING_EDGES
Input 6 rising edges.
0xC
INPUT_6_FALLING_EDGE
Input 6 falling edges.
0xD
INPUT_7_RISING_EDGES
Input 7 rising edges.
0xE
INPUT_7_FALLING_EDGE
Input 7 falling edges.
0xF
CLKMODE
SCT clock mode
1
3
ENUM
SYSTEM_CLOCK
System clock. The system clock clocks the SCT and
prescalers.
0x0
PRESCALED_SYSTEM_CLO
Prescaled system clock. The SCT clock is the system
clock, but the prescalers are enabled to count only when
sampling of the input selected by the CKSEL field finds the
selected edge. The minimum pulse width on the clock input is
1 bus clock period. This mode is the high-performance
sampled-clock mode.
0x1
SCT_INPUT
SCT input. The input selected by CKSEL clocks the
SCT and prescalers. The input is synchronized to the system
clock and possibly inverted. The minimum pulse width on the
clock input is 1 bus clock period. This mode is the
low-power sampled-clock mode.
0x2
PRESCALED_SCT_INPUT
Prescaled SCT input. The SCT and prescalers are
clocked by the input edge selected by the CKSEL field. In
this mode, most of the SCT is clocked by the (selected
polarity of the) input. The outputs are switched
synchronously to the input clock. The input clock rate must
be at least half the system clock rate and can be the same
or faster than the system clock.
0x3
INSYNC
Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 14 = input 5). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CLKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.
9
15
NORELOAD_H
A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
8
9
NORELOAD_L
A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
15
17
RESERVED
Reserved. Read value is undefined, only zero should be written.
15
17
UNIFY
SCT operation
0
1
ENUM
DUAL_COUNTER
Dual counter. The SCT operates as two 16-bit
counters named L and H.
0
UNIFIED_COUNTER
Unified counter. The SCT operates as a unified
32-bit counter.
1
CONFLAG
SCT conflict flag register
0xFC
read-write
n
0x0
0x0
BUSERRH
The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.
31
32
BUSERRL
The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.
30
31
NCFLAG
Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.
0
8
RESERVED
Reserved.
10
30
COUNT
SCT counter register
0x40
read-write
n
0x0
0x0
CTR_H
When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.
16
32
CTR_L
When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.
0
16
CTRL
SCT control register
0x4
read-write
n
0x0
0x0
BIDIR_H
Direction select
20
21
ENUM
UNIDIRECTIONAL
Unidirectional. The H counter counts up to its
limit condition, then is cleared to zero.
0
BIDIRECTIONAL
Bidirectional. The H counter counts up to its
limit, then counts down to a limit condition or to
0.
1
BIDIR_L
L or unified counter direction select
4
5
ENUM
UNIDIRECTIONAL
Unidirectional. The counter counts up to its limit
condition, then is cleared to zero.
0
BIDIRECTIONAL
Bidirectional. The counter counts up to its limit,
then counts down to a limit condition or to 0.
1
CLRCTR_H
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
19
20
CLRCTR_L
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
3
4
DOWN_H
This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs.
16
17
DOWN_L
This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs.
0
1
HALT_H
When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. In order to remove the halt condition and keep the SCT in the stop condition (not running), the halt and stop condition can be changed with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation.
18
19
HALT_L
When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. In order to remove the halt condition and keep the SCT in the stop condition (not running), the halt and stop condition can be changed with one single write to this register. Once set, only software can clear this bit to restore counter operation.
2
3
PRE_H
Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
21
29
PRE_L
Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
5
13
RESERVED
Reserved. Read value is undefined, only zero should be written.
13
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
13
16
STOP_H
When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
17
18
STOP_L
When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
1
2
DMAREQ0
SCT DMA request 0 register
0x5C
read-write
n
0x0
0x0
DEV_0
If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
DRL0
A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers.
30
31
DRQ0
This read-only bit indicates the state of DMA Request 0
31
32
RESERVED
Reserved
16
30
DMAREQ1
SCT DMA request 1 register
0x60
read-write
n
0x0
0x0
DEV_1
If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
DRL1
A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
30
31
DRQ1
This read-only bit indicates the state of DMA Request 1.
31
32
RESERVED
Reserved
16
30
EV0_CTRL
SCT event control register 0
0x608
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV0_STATE
SCT event state register 0
0x600
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV10_CTRL
SCT event control register 0
0x25E8
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV10_STATE
SCT event state register 0
0x25B8
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV11_CTRL
SCT event control register 0
0x2944
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV11_STATE
SCT event state register 0
0x2910
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV12_CTRL
SCT event control register 0
0x2CA8
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV12_STATE
SCT event state register 0
0x2C70
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV1_CTRL
SCT event control register 0
0x914
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV1_STATE
SCT event state register 0
0x908
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV2_CTRL
SCT event control register 0
0xC28
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV2_STATE
SCT event state register 0
0xC18
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV3_CTRL
SCT event control register 0
0xF44
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV3_STATE
SCT event state register 0
0xF30
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV4_CTRL
SCT event control register 0
0x1268
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV4_STATE
SCT event state register 0
0x1250
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV5_CTRL
SCT event control register 0
0x1594
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV5_STATE
SCT event state register 0
0x1578
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV6_CTRL
SCT event control register 0
0x18C8
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV6_STATE
SCT event state register 0
0x18A8
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV7_CTRL
SCT event control register 0
0x1C04
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV7_STATE
SCT event state register 0
0x1BE0
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV8_CTRL
SCT event control register 0
0x1F48
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV8_STATE
SCT event state register 0
0x1F20
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EV9_CTRL
SCT event control register 0
0x2294
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
14
ENUM
OR
OR. The event occurs when either the specified
match or I/O condition occurs.
0x0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition
only.
0x2
AND
AND. The event occurs when the specified match and
I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
23
ENUM
DIRECTION_INDEPENDEN
Direction independent. This event is triggered
regardless of the count direction.
0x0
COUNTING_UP
Counting up. This event is triggered only during
up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during
down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
5
ENUM
L_COUNTER
L counter. Selects the L state and the L match
register selected by MATCHSEL.
0
H_COUNTER
H counter. Selects the H state and the H match
register selected by MATCHSEL.
1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
12
ENUM
LOW
LOW
0x0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CLKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
10
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
21
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
OUTSEL
Input/output select
5
6
ENUM
INPUT
Input. Selects the input selected by
IOSEL.
0
OUTPUT
Output. Selects the output selected by
IOSEL.
1
RESERVED
Reserved
23
32
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
15
ENUM
ADD
Add. STATEV value is added into STATE (the
carry-out is ignored).
0
LOAD
Load. STATEV value is loaded into
STATE.
1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
20
EV9_STATE
SCT event state register 0
0x2268
read-write
n
0x0
0x0
STATEMSKn
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1, etc. The number of bits = number of events in this SCT.
0
13
EVEN
SCT event enable register
0xF0
read-write
n
0x0
0x0
IEN
The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.
0
16
RESERVED
Reserved
16
32
EVFLAG
SCT event flag register
0xF4
read-write
n
0x0
0x0
FLAG
Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
HALT
SCT halt condition register
0xC
read-write
n
0x0
0x0
HALTMSK_H
If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
HALTMSK_L
If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
INPUT
SCT input register
0x48
read-only
n
0x0
0x0
AIN0
Input 0 state.Direct read.
0
1
AIN1
Input 1 state. Direct read.
1
2
AIN2
Input 2 state. Direct read.
2
3
AIN3
Input 3 state. Direct read.
3
4
AIN4
Input 4 state. Direct read.
4
5
AIN5
Input 5 state. Direct read.
5
6
RESERVED
Reserved.
6
16
RESERVED
Reserved.
6
16
SIN0
Input 0 state.
16
17
SIN1
Input 1 state.
17
18
SIN2
Input 2 state.
18
19
SIN3
Input 3 state.
19
20
SIN4
Input 4 state.
20
21
SIN5
Input 5 state.
21
22
LIMIT
SCT limit register
0x8
read-write
n
0x0
0x0
LIMMSK_H
If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
LIMMSK_L
If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
MATCH0
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0x200
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH1
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0x304
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH10
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0xCDC
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH11
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0xE08
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH12
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0xF38
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH2
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0x40C
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH3
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0x518
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH4
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0x628
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH5
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0x73C
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH6
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0x854
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH7
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0x970
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH8
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0xA90
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCH9
SCT match value register of match channels 0 to 12; REGMOD0 to REGMODE12 = 0
0xBB4
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
32
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
MATCHREL0
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x400
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL1
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x604
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL10
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x18DC
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL11
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x1B08
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL12
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x1D38
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL2
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x80C
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL3
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0xA18
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL4
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0xC28
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL5
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0xE3C
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL6
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x1054
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL7
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x1270
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL8
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x1490
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
MATCHREL9
SCT match reload value register 0 to 12; REGMOD0 = 0 to REGMODE12 = 0
0x16B4
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
32
RELOADn_L
When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
OUT0_CLR
SCT output 0 clear register
0xA08
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
OUT0_SET
SCT output 0 set register
0xA00
read-write
n
0x0
0x0
RESERVED
Reserved
16
32
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
OUT1_CLR
SCT output 0 clear register
0xF14
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
OUT1_SET
SCT output 0 set register
0xF08
read-write
n
0x0
0x0
RESERVED
Reserved
16
32
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
OUT2_CLR
SCT output 0 clear register
0x1428
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
OUT2_SET
SCT output 0 set register
0x1418
read-write
n
0x0
0x0
RESERVED
Reserved
16
32
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
OUT3_CLR
SCT output 0 clear register
0x1944
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
OUT3_SET
SCT output 0 set register
0x1930
read-write
n
0x0
0x0
RESERVED
Reserved
16
32
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
OUT4_CLR
SCT output 0 clear register
0x1E68
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
OUT4_SET
SCT output 0 set register
0x1E50
read-write
n
0x0
0x0
RESERVED
Reserved
16
32
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
OUT5_CLR
SCT output 0 clear register
0x2394
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
OUT5_SET
SCT output 0 set register
0x2378
read-write
n
0x0
0x0
RESERVED
Reserved
16
32
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
OUT6_CLR
SCT output 0 clear register
0x28C8
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
OUT6_SET
SCT output 0 set register
0x28A8
read-write
n
0x0
0x0
RESERVED
Reserved
16
32
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
OUT7_CLR
SCT output 0 clear register
0x2E04
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
RESERVED
Reserved
16
32
OUT7_SET
SCT output 0 set register
0x2DE0
read-write
n
0x0
0x0
RESERVED
Reserved
16
32
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
OUTPUT
SCT output register
0x50
read-write
n
0x0
0x0
OUT
Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.
0
8
RESERVED
Reserved
8
32
OUTPUTDIRCTRL
SCT output counter direction control register
0x54
read-write
n
0x0
0x0
RESERVED
Reserved.
26
32
SETCLR0
Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
0
2
ENUM
INDEPENDENT
Independent. Set and clear do not depend on any
counter.
0x0
L_REVERSED
L-Reversed. Set and clear are reversed when counter
L or the unified counter is counting down.
0x1
H_REVERSED
H-Reversed. Set and clear are reversed when counter
H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR1
Set/clear operation on output 1. See description of bit 0.
2
4
SETCLR2
Set/clear operation on output 2. See description of bit 0.
4
6
SETCLR3
Set/clear operation on output 3. See description of bit 0.
6
8
SETCLR4
Set/clear operation on output 4. See description of bit 0.
8
10
SETCLR5
Set/clear operation on output 5. See description of bit 0.
10
12
SETCLR6
Set/clear operation on output 6. See description of bit 0.
12
14
SETCLR7
Set/clear operation on output 7. See description of bit 0.
14
16
REGMODE
SCT match/capture registers mode register
0x4C
read-write
n
0x0
0x0
REGMOD_H
Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17, etc. 0 = registers operate as match registers. 1 = registers operate as capture registers.
16
32
REGMOD_L
Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., etc. 0 = registers operate as match registers. 1 = registers operate as capture registers.
0
16
RES
SCT conflict resolution register
0x58
read-write
n
0x0
0x0
O0RES
Effect of simultaneous set and clear on output 0.
0
2
ENUM
NO_CHANGE
No change.
0x0
SET
Set. Set output (or clear based on the SETCLR0
field).
0x1
CLEAR
Clear. Clear output (or set based on the SETCLR0
field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O1RES
Effect of simultaneous set and clear on output 1.
2
4
ENUM
NO_CHANGE
No change.
0x0
SET
Set. Set output (or clear based on the SETCLR1
field).
0x1
CLEAR
Clear. Clear output (or set based on the SETCLR1
field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O2RES
Effect of simultaneous set and clear on output 2.
4
6
ENUM
NO_CHANGE
No change.
0x0
SET
Set. Set output (or clear based on the SETCLR2
field).
0x1
CLEAR
Clear. Clear output (or set based on the SETCLR2
field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O3RES
Effect of simultaneous set and clear on output 3.
6
8
ENUM
NO_CHANGE
No change.
0x0
SET
Set. Set output (or clear based on the SETCLR3
field).
0x1
CLEAR
Clear. Clear output (or set based on the SETCLR3
field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O4RES
Effect of simultaneous set and clear on output 4.
8
10
ENUM
NO_CHANGE
No change.
0x0
SET
Set. Set output (or clear based on the SETCLR4
field).
0x1
CLEAR
Clear. Clear output (or set based on the SETCLR4
field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O5RES
Effect of simultaneous set and clear on output 5.
10
12
ENUM
NO_CHANGE
No change.
0x0
SET
Set. Set output (or clear based on the SETCLR5
field).
0x1
CLEAR
Clear. Clear output (or set based on the SETCLR5
field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O6RES
Effect of simultaneous set and clear on output 6.
12
14
ENUM
NO_CHANGE
No change.
0x0
SET
Set. Set output (or clear based on the SETCLR6
field).
0x1
CLEAR
Clear. Clear output (or set based on the SETCLR6
field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O7RES
Effect of simultaneous set and clear on output 7.
14
16
ENUM
NO_CHANGE
No change.
0x0
SET
Set. Set output (or clear based on the SETCLR7
field).
0x1
CLEAR
Clear. Clear output (or set based on the SETCLR7
field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
RESERVED
Reserved.
16
32
START
SCT start condition register
0x14
read-write
n
0x0
0x0
STARTMSK_H
If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
STARTMSK_L
If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
STATE
SCT state register
0x44
read-write
n
0x0
0x0
RESERVED
Reserved.
5
16
RESERVED
Reserved.
5
16
STATE_H
State variable.
16
21
STATE_L
State variable.
0
5
STOP
SCT stop condition register
0x10
read-write
n
0x0
0x0
STOPMSK_H
If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc. The number of bits = number of events in this SCT.
16
32
STOPMSK_L
If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT.
0
16
SPI0
SPI0
SPI0
0x0
0x0
0x1000
registers
n
SPI0
24
CFG
SPI Configuration register
0x0
read-write
n
0x0
0x0
CPHA
Clock Phase select.
4
5
ENUM
CHANGE
Change. The SPI captures serial data on the first
clock transition of the transfer (when the clock changes
away from the rest state). Data is changed on the following
edge.
0
CAPTURE
Capture. The SPI changes serial data on the first
clock transition of the transfer (when the clock changes
away from the rest state). Data is captured on the following
edge.
1
CPOL
Clock Polarity select.
5
6
ENUM
LOW
Low. The rest state of the clock (between
transfers) is low.
0
HIGH
High. The rest state of the clock (between
transfers) is high.
1
ENABLE
SPI enable.
0
1
ENUM
DISABLED
Disabled. The SPI is disabled and the internal
state machine and counters are reset.
0
ENABLED
Enabled. The SPI is enabled for
operation.
1
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
7
8
ENUM
DISABLED
Disabled.
0
ENABLED
Enabled.
1
LSBF
LSB First mode enable.
3
4
ENUM
STANDARD
Standard. Data is transmitted and received in
standard MSB first order.
0
REVERSE
Reverse. Data is transmitted and received in
reverse order (LSB first).
1
MASTER
Master mode select.
2
3
ENUM
SLAVE_MODE
Slave mode. The SPI will operate in slave mode.
SCK, MOSI, and the SSEL signals are inputs, MISO is an
output.
0
MASTER_MODE
Master mode. The SPI will operate in master mode.
SCK, MOSI, and the SSEL signals are outputs, MISO is an
input.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
7
SPOL0
SSEL0 Polarity select.
8
9
ENUM
LOW
Low. The SSEL0 pin is active low. The value in the
SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL0 is not inverted relative to the
pins.
0
HIGH
High. The SSEL0 pin is active high. The value in
the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL0 is inverted relative to the
pins.
1
SPOL1
SSEL1 Polarity select.
9
10
ENUM
LOW
Low. The SSEL1 pin is active low. The value in the
SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL1 is not inverted relative to the
pins.
0
HIGH
High. The SSEL1 pin is active high. The value in
the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL1 is inverted relative to the
pins.
1
SPOL2
SSEL2 Polarity select.
10
11
ENUM
LOW
Low. The SSEL2 pin is active low. The value in the
SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL2 is not inverted relative to the
pins.
0
HIGH
High. The SSEL2 pin is active high. The value in
the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL2 is inverted relative to the
pins.
1
SPOL3
SSEL3 Polarity select.
11
12
ENUM
LOW
Low. The SSEL3 pin is active low. The value in the
SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL3 is not inverted relative to the
pins.
0
HIGH
High. The SSEL3 pin is active high. The value in
the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL3 is inverted relative to the
pins.
1
DIV
SPI clock Divider
0x24
read-write
n
0x0
0x0
DIVVAL
Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
DLY
SPI Delay register
0x4
read-write
n
0x0
0x0
FRAME_DELAY
If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
8
12
POST_DELAY
Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
4
8
PRE_DELAY
Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
TRANSFER_DELAY
Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
12
16
INTENCLR
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
0x10
write-only
n
0x0
0x0
MSTIDLE
Writing 1 clears the corresponding bits in the MSTIDLE register.
8
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RXOVEN
Writing 1 clears the corresponding bits in the INTENSET register.
2
3
RXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
1
SSAEN
Writing 1 clears the corresponding bits in the INTENSET register.
4
5
SSDEN
Writing 1 clears the corresponding bits in the INTENSET register.
5
6
TXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
1
2
TXUREN
Writing 1 clears the corresponding bits in the INTENSET register.
3
4
INTENSET
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
read-write
n
0x0
0x0
MSTIDLEEN
Master idle interrupt enable
8
9
ENUM
DISABLED
Disabled. No interrupt will be generated when the
SPI master function is idle.
0
ENABLED
Enabled. An interrupt will be generated when the
SPI master function is idle.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RXOVEN
RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
2
3
ENUM
DISABLED
Disabled. No interrupt will be generated when a
receiver overrun occurs.
0
ENABLED
Enabled. An interrupt will be generated if a
receiver overrun occurs.
1
RXRDYEN
RX ready interrupt enable. Determines whether an interrupt occurs when receiver data is available.
0
1
ENUM
DISABLED
Disabled. No interrupt will be generated when
receiver data is available.
0
ENABLED
Enabled. An interrupt will be generated when
receiver data is available in the RXDAT
register.
1
SSAEN
Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
4
5
ENUM
DISABLED
Disabled. No interrupt will be generated when any
Slave Select transitions from deasserted to
asserted.
0
ENABLED
Enabled. An interrupt will be generated when any
Slave Select transitions from deasserted to
asserted.
1
SSDEN
Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
5
6
ENUM
DISABLED
Disabled. No interrupt will be generated when all
asserted Slave Selects transition to
deasserted.
0
ENABLED
Enabled. An interrupt will be generated when all
asserted Slave Selects transition to
deasserted.
1
TXRDYEN
TX ready interrupt enable. Determines whether an interrupt occurs when the transmitter holding register is available.
1
2
ENUM
DISABLED
Disabled. No interrupt will be generated when the
transmitter holding register is available.
0
ENABLED
Enabled. An interrupt will be generated when data
may be written to TXDAT.
1
TXUREN
TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
3
4
ENUM
DISABLED
Disabled. No interrupt will be generated when the
transmitter underruns.
0
ENABLED
Enabled. An interrupt will be generated if the
transmitter underruns.
1
INTSTAT
SPI Interrupt Status
0x28
read-only
n
0x0
0x0
MSTIDLE
Master Idle status flag.
8
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RXOV
Receiver Overrun interrupt flag.
2
3
RXRDY
Receiver Ready flag.
0
1
SSA
Slave Select Assert.
4
5
SSD
Slave Select Deassert.
5
6
TXRDY
Transmitter Ready flag.
1
2
TXUR
Transmitter Underrun interrupt flag.
3
4
RXDAT
SPI Receive Data
0x14
read-only
n
0x0
0x0
modify
RESERVED
Reserved, the value read from a reserved bit is not defined.
21
32
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
17
RXSSEL1_N
Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
17
18
RXSSEL2_N
Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
18
19
RXSSEL3_N
Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
19
20
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
21
STAT
SPI Status. Some status flags can be cleared by writing a 1 to that bit position
0x8
read-write
n
0x0
0x0
ENDTRANSFER
End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
7
8
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
8
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
32
RXOV
Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
2
3
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
0
1
SSA
Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
4
5
SSD
Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
5
6
STALLED
Stalled status flag. This indicates whether the SPI is currently in a stall condition.
6
7
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
1
2
TXUR
Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
3
4
TXCTL
SPI Transmit Control
0x20
read-write
n
0x0
0x0
EOF
End of Frame.
21
22
EOT
End of Transfer.
20
21
LEN
Data transfer Length.
24
28
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RXIGNORE
Receive Ignore.
22
23
TXSSEL0_N
Transmit Slave Select 0.
16
17
TXSSEL1_N
Transmit Slave Select 1.
17
18
TXSSEL2_N
Transmit Slave Select 2.
18
19
TXSSEL3_n
Transmit Slave Select 3.
19
20
TXDAT
SPI Transmit Data
0x1C
read-write
n
0x0
0x0
DATA
Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
0
16
RESERVED
Reserved. Only zero should be written.
16
32
TXDATCTL
SPI Transmit Data with Control
0x18
read-write
n
0x0
0x0
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
22
ENUM
DATA_NOT_EOF
Data not EOF. This piece of data transmitted is not
treated as the end of a frame.
0
DATA_EOF
Data EOF. This piece of data is treated as the end
of a frame, causing the FRAME_DELAY time to be inserted
before subsequent data is transmitted.
1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
21
ENUM
SSEL_NOT_DEASSERTED
SSEL not deasserted. This piece of data is not
treated as the end of a transfer. SSEL will not be
deasserted at the end of this data.
0
SSEL_DEASSERTED
SSEL deasserted. This piece of data is treated as
the end of a transfer. SSEL will be deasserted at the end of
this piece of data.
1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
28
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
22
23
ENUM
READ_RECEIVED_DATA
Read received data. Received data must be read in
order to allow transmission to progress. In slave mode, an
overrun error will occur if received data is not read before
new data is received.
0
IGNORE_RECEIVED_DATA
Ignore received data. Received data is ignored,
allowing transmission without reading unneeded received
data. No receiver flags are generated.
1
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register.
16
17
ENUM
SSEL0_ASSERTED
SSEL0 asserted.
0
SSEL0_NOT_ASSERTED
SSEL0 not asserted.
1
TXSSEL1_N
Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register.
17
18
ENUM
SSEL1_ASSERTED
SSEL1 asserted.
0
SSEL1_NOT_ASSERTED
SSEL1 not asserted.
1
TXSSEL2_N
Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register.
18
19
ENUM
SSEL2_ASSERTED
SSEL2 asserted.
0
SSEL2_NOT_ASSERTED
SSEL2 not asserted.
1
TXSSEL3_N
Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register.
19
20
ENUM
SSEL3_ASSERTED
SSEL3 asserted.
0
SSEL3_NOT_ASSERTED
SSEL3 not asserted.
1
SPI1
SPI1
SPI0
0x0
0x0
0x1000
registers
n
SPI1
25
CFG
SPI Configuration register
0x0
read-write
n
0x0
0x0
CPHA
Clock Phase select.
4
5
ENUM
CHANGE
Change. The SPI captures serial data on the first
clock transition of the transfer (when the clock changes
away from the rest state). Data is changed on the following
edge.
0
CAPTURE
Capture. The SPI changes serial data on the first
clock transition of the transfer (when the clock changes
away from the rest state). Data is captured on the following
edge.
1
CPOL
Clock Polarity select.
5
6
ENUM
LOW
Low. The rest state of the clock (between
transfers) is low.
0
HIGH
High. The rest state of the clock (between
transfers) is high.
1
ENABLE
SPI enable.
0
1
ENUM
DISABLED
Disabled. The SPI is disabled and the internal
state machine and counters are reset.
0
ENABLED
Enabled. The SPI is enabled for
operation.
1
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
7
8
ENUM
DISABLED
Disabled.
0
ENABLED
Enabled.
1
LSBF
LSB First mode enable.
3
4
ENUM
STANDARD
Standard. Data is transmitted and received in
standard MSB first order.
0
REVERSE
Reverse. Data is transmitted and received in
reverse order (LSB first).
1
MASTER
Master mode select.
2
3
ENUM
SLAVE_MODE
Slave mode. The SPI will operate in slave mode.
SCK, MOSI, and the SSEL signals are inputs, MISO is an
output.
0
MASTER_MODE
Master mode. The SPI will operate in master mode.
SCK, MOSI, and the SSEL signals are outputs, MISO is an
input.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
7
SPOL0
SSEL0 Polarity select.
8
9
ENUM
LOW
Low. The SSEL0 pin is active low. The value in the
SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL0 is not inverted relative to the
pins.
0
HIGH
High. The SSEL0 pin is active high. The value in
the SSEL0 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL0 is inverted relative to the
pins.
1
SPOL1
SSEL1 Polarity select.
9
10
ENUM
LOW
Low. The SSEL1 pin is active low. The value in the
SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL1 is not inverted relative to the
pins.
0
HIGH
High. The SSEL1 pin is active high. The value in
the SSEL1 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL1 is inverted relative to the
pins.
1
SPOL2
SSEL2 Polarity select.
10
11
ENUM
LOW
Low. The SSEL2 pin is active low. The value in the
SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL2 is not inverted relative to the
pins.
0
HIGH
High. The SSEL2 pin is active high. The value in
the SSEL2 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL2 is inverted relative to the
pins.
1
SPOL3
SSEL3 Polarity select.
11
12
ENUM
LOW
Low. The SSEL3 pin is active low. The value in the
SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL3 is not inverted relative to the
pins.
0
HIGH
High. The SSEL3 pin is active high. The value in
the SSEL3 fields of the RXDAT, TXDATCTL, and TXCTL registers
related to SSEL3 is inverted relative to the
pins.
1
DIV
SPI clock Divider
0x24
read-write
n
0x0
0x0
DIVVAL
Rate divider value. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
DLY
SPI Delay register
0x4
read-write
n
0x0
0x0
FRAME_DELAY
If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
8
12
POST_DELAY
Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
4
8
PRE_DELAY
Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
TRANSFER_DELAY
Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
12
16
INTENCLR
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
0x10
write-only
n
0x0
0x0
MSTIDLE
Writing 1 clears the corresponding bits in the MSTIDLE register.
8
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RXOVEN
Writing 1 clears the corresponding bits in the INTENSET register.
2
3
RXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
1
SSAEN
Writing 1 clears the corresponding bits in the INTENSET register.
4
5
SSDEN
Writing 1 clears the corresponding bits in the INTENSET register.
5
6
TXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
1
2
TXUREN
Writing 1 clears the corresponding bits in the INTENSET register.
3
4
INTENSET
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
read-write
n
0x0
0x0
MSTIDLEEN
Master idle interrupt enable
8
9
ENUM
DISABLED
Disabled. No interrupt will be generated when the
SPI master function is idle.
0
ENABLED
Enabled. An interrupt will be generated when the
SPI master function is idle.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RXOVEN
RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
2
3
ENUM
DISABLED
Disabled. No interrupt will be generated when a
receiver overrun occurs.
0
ENABLED
Enabled. An interrupt will be generated if a
receiver overrun occurs.
1
RXRDYEN
RX ready interrupt enable. Determines whether an interrupt occurs when receiver data is available.
0
1
ENUM
DISABLED
Disabled. No interrupt will be generated when
receiver data is available.
0
ENABLED
Enabled. An interrupt will be generated when
receiver data is available in the RXDAT
register.
1
SSAEN
Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
4
5
ENUM
DISABLED
Disabled. No interrupt will be generated when any
Slave Select transitions from deasserted to
asserted.
0
ENABLED
Enabled. An interrupt will be generated when any
Slave Select transitions from deasserted to
asserted.
1
SSDEN
Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
5
6
ENUM
DISABLED
Disabled. No interrupt will be generated when all
asserted Slave Selects transition to
deasserted.
0
ENABLED
Enabled. An interrupt will be generated when all
asserted Slave Selects transition to
deasserted.
1
TXRDYEN
TX ready interrupt enable. Determines whether an interrupt occurs when the transmitter holding register is available.
1
2
ENUM
DISABLED
Disabled. No interrupt will be generated when the
transmitter holding register is available.
0
ENABLED
Enabled. An interrupt will be generated when data
may be written to TXDAT.
1
TXUREN
TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
3
4
ENUM
DISABLED
Disabled. No interrupt will be generated when the
transmitter underruns.
0
ENABLED
Enabled. An interrupt will be generated if the
transmitter underruns.
1
INTSTAT
SPI Interrupt Status
0x28
read-only
n
0x0
0x0
MSTIDLE
Master Idle status flag.
8
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RXOV
Receiver Overrun interrupt flag.
2
3
RXRDY
Receiver Ready flag.
0
1
SSA
Slave Select Assert.
4
5
SSD
Slave Select Deassert.
5
6
TXRDY
Transmitter Ready flag.
1
2
TXUR
Transmitter Underrun interrupt flag.
3
4
RXDAT
SPI Receive Data
0x14
read-only
n
0x0
0x0
modify
RESERVED
Reserved, the value read from a reserved bit is not defined.
21
32
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
17
RXSSEL1_N
Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
17
18
RXSSEL2_N
Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
18
19
RXSSEL3_N
Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
19
20
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
21
STAT
SPI Status. Some status flags can be cleared by writing a 1 to that bit position
0x8
read-write
n
0x0
0x0
ENDTRANSFER
End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
7
8
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
8
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
32
RXOV
Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
2
3
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
0
1
SSA
Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
4
5
SSD
Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
5
6
STALLED
Stalled status flag. This indicates whether the SPI is currently in a stall condition.
6
7
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
1
2
TXUR
Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
3
4
TXCTL
SPI Transmit Control
0x20
read-write
n
0x0
0x0
EOF
End of Frame.
21
22
EOT
End of Transfer.
20
21
LEN
Data transfer Length.
24
28
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RXIGNORE
Receive Ignore.
22
23
TXSSEL0_N
Transmit Slave Select 0.
16
17
TXSSEL1_N
Transmit Slave Select 1.
17
18
TXSSEL2_N
Transmit Slave Select 2.
18
19
TXSSEL3_n
Transmit Slave Select 3.
19
20
TXDAT
SPI Transmit Data
0x1C
read-write
n
0x0
0x0
DATA
Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
0
16
RESERVED
Reserved. Only zero should be written.
16
32
TXDATCTL
SPI Transmit Data with Control
0x18
read-write
n
0x0
0x0
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
22
ENUM
DATA_NOT_EOF
Data not EOF. This piece of data transmitted is not
treated as the end of a frame.
0
DATA_EOF
Data EOF. This piece of data is treated as the end
of a frame, causing the FRAME_DELAY time to be inserted
before subsequent data is transmitted.
1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
21
ENUM
SSEL_NOT_DEASSERTED
SSEL not deasserted. This piece of data is not
treated as the end of a transfer. SSEL will not be
deasserted at the end of this data.
0
SSEL_DEASSERTED
SSEL deasserted. This piece of data is treated as
the end of a transfer. SSEL will be deasserted at the end of
this piece of data.
1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
28
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
22
23
ENUM
READ_RECEIVED_DATA
Read received data. Received data must be read in
order to allow transmission to progress. In slave mode, an
overrun error will occur if received data is not read before
new data is received.
0
IGNORE_RECEIVED_DATA
Ignore received data. Received data is ignored,
allowing transmission without reading unneeded received
data. No receiver flags are generated.
1
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register.
16
17
ENUM
SSEL0_ASSERTED
SSEL0 asserted.
0
SSEL0_NOT_ASSERTED
SSEL0 not asserted.
1
TXSSEL1_N
Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register.
17
18
ENUM
SSEL1_ASSERTED
SSEL1 asserted.
0
SSEL1_NOT_ASSERTED
SSEL1 not asserted.
1
TXSSEL2_N
Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register.
18
19
ENUM
SSEL2_ASSERTED
SSEL2 asserted.
0
SSEL2_NOT_ASSERTED
SSEL2 not asserted.
1
TXSSEL3_N
Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register.
19
20
ENUM
SSEL3_ASSERTED
SSEL3 asserted.
0
SSEL3_NOT_ASSERTED
SSEL3 not asserted.
1
SYSCON
System configuration
SYSCON
0x0
0x0
0x1000
registers
n
ADCCLKDIV
ADC clock divider
0x108
read-write
n
0x0
0x0
DIV
ADC clock divider value. 0: Disable ADC clock. 1: Divide by 1. to 255: Divide by 255.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
ADCCLKSEL
ADC clock source select
0x8C
read-write
n
0x0
0x0
RESERVED
Reserved
2
32
SEL
ADC clock source.
0
2
ENUM
MAIN_CLOCK
Main clock
0x0
SYSTEM_PLL_OUTPUT
System PLL output
0x1
IRC_OSCILLATOR
IRC Oscillator
0x2
RESERVED
reserved
0x3
AHBCLKCTRL0
AHB Clock control 0
0xC0
read-write
n
0x0
0x0
ADC0
Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable.
27
28
CRC
Enables the clock for the CRC engine. 0 = Disable; 1 = Enable.
21
22
DMA
Enables the clock for the DMA controller. 0 = Disable; 1 = Enable.
20
21
FLASH
Enables the clock for the flash controller. 0 = Disable; 1 = Enable.
7
8
FMC
Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable.
8
9
GINT
Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable.
19
20
GPIO0
Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable.
14
15
GPIO1
Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable.
15
16
INPUTMUX
Enables the clock for the input muxes. 0 = Disable; 1 = Enable.
11
12
IOCON
Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.
13
14
MAILBOX
Enables the clock for the Mailbox. 0 = Disable; 1 = Enable.
26
27
PINT
Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
3
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
13
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
18
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
26
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
26
ROM
Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable.
1
2
RTC
Enables the clock for the RTC. 0 = Disable; 1 = Enable.
23
24
SRAM1
Enables the clock for SRAM1. 0 = Disable; 1 = Enable.
3
4
SRAM2
Enables the clock for SRAM2. 0 = Disable; 1 = Enable.
4
5
WWDT
Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable.
22
23
AHBCLKCTRL1
AHB Clock control 1
0xC4
read-write
n
0x0
0x0
FIFO
Enables the clock for system FIFOs. 0 = Disable; 1 = Enable.
9
10
MRT
Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
11
22
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
26
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
26
RIT
Enables the clock for the repetitive interrupt timer. 0 = Disable; 1 = Enable.
1
2
SCT0
Enables the clock for SCT0. 0 = Disable; 1 = Enable.
2
3
TIMER2
Enables the clock for Timer 2. 0 = Disable; 1 = Enable.
22
23
TIMER3
Enables the clock for Timer 3. 0 = Disable; 1 = Enable.
26
27
TIMER4
Enables the clock for Timer 4. 0 = Disable; 1 = Enable.
27
28
UTICK
Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable.
10
11
AHBCLKCTRLCLR0
Clear bits in AHBCLKCTRL0
0xD0
write-only
n
0x0
0x0
CLK_CLR0
Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL0 register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them.
0
32
AHBCLKCTRLCLR1
Clear bits in AHBCLKCTRL1
0xD4
write-only
n
0x0
0x0
CLK_CLR1
Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL1 register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL1 are reserved and only zeroes should be written to them.
0
32
AHBCLKCTRLSET0
Set bits in AHBCLKCTRL0
0xC8
write-only
n
0x0
0x0
CLK_SET0
Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRL0 register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL0 are reserved and only zeroes should be written to them.
0
32
AHBCLKCTRLSET1
Set bits in AHBCLKCTRL1
0xCC
write-only
n
0x0
0x0
CLK_SET1
Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRL1 register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRL1 are reserved and only zeroes should be written to them.
0
32
AHBCLKDIV
System clock divider
0x100
read-write
n
0x0
0x0
DIV
System AHB clock divider value. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
AHBMATPRIO
AHB multilayer matrix priority control
0x4
read-write
n
0x0
0x0
PRI_DCODE
D-Code bus priority.
2
4
PRI_DMA
DMA controller priority.
8
10
PRI_FIFO
System FIFO bus priority
14
16
PRI_ICODE
I-Code bus priority. Should be lower than PRI_DCODE for proper operation.
0
2
PRI_M0
Cortex-M0+ bus priority.
16
18
PRI_SYS
System bus priority.
4
6
RESERVED
Reserved. Read value is undefined, only zero should be written..
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written..
10
14
RESERVED
Reserved. Read value is undefined, only zero should be written..
10
14
ASYNCAPBCTRL
Asynchronous APB Control
0x20
read-write
n
0x0
0x0
ENABLE
Enables the asynchronous APB bridge and subsystem.
0
1
ENUM
DISABLED
Disabled. Asynchronous APB bridge is
disabled.
0
ENABLED
Enabled. Asynchronous APB bridge is
enabled.
1
RESERVED
Reserved. Read value is undefined, only zero should be written..
1
32
CLKOUTDIV
CLKOUT clock divider
0x10C
read-write
n
0x0
0x0
DIV
CLKOUT clock divider value. 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
CLKOUTSELA
CLKOUT clock source select A
0x94
read-write
n
0x0
0x0
RESERVED
Reserved
2
32
SEL
CLKOUT clock source
0
2
ENUM
MAIN_CLOCK
Main clock
0x0
CLKIN
CLKIN
0x1
WATCHDOG_OSCILLATOR
Watchdog oscillator
0x2
IRC_OSCILLATOR
IRC oscillator
0x3
CLKOUTSELB
CLKOUT clock source select B
0x98
read-write
n
0x0
0x0
RESERVED
Reserved
2
32
SEL
CLKOUT clock source
0
2
ENUM
CLKOUTSELA
CLKOUTSELA. Clock source selected in the CLKOUTSELA
register.
0x0
RESERVED
reserved
0x1
RESERVED
reserved
0x1
RTC_32_KHZ_CLOCK
RTC 32 kHz clock
0x3
CPBOOT
Coprocessor Boot Address
0x304
read-write
n
0x0
0x0
BOOTADDR
Slave processor boot address.
0
32
CPSTACK
Coprocessor Stack Address
0x308
read-write
n
0x0
0x0
STACKADDR
Slave processor stack address.
0
32
CPUCTRL
CPU Control for multiple processors
0x300
read-write
n
0x0
0x0
CM0CLKEN
Cortex-M0+ clock enable.
3
4
ENUM
DISABLED
Disabled. The Cortex-M0+ clock is not
enabled.
0
ENABLED
Enabled. The Cortex-M0+ clock is
enabled.
1
CM0RSTEN
Cortex-M0+ reset.
5
6
ENUM
DISABLED
Disabled. The Cortex-M0+ is not being
reset.
0
ENABLED
Enabled. The Cortex-M0+ is being
reset.
1
CM4CLKEN
Cortex-M4 clock enable.
2
3
ENUM
DISABLED
Disabled. The Cortex-M4 clock is not
enabled.
0
ENABLED
Enabled. The Cortex-M4 clock is
enabled.
1
CM4RSTEN
Cortex-M4 reset.
4
5
ENUM
DISABLED
Disabled. The Cortex-M4 is not being
reset.
0
ENABLED
Enabled. The Cortex-M4 is being
reset.
1
MASTERCPU
Determines which CPU is considered the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit or be reset via the related CMxRSTEN in this register. The slave CPU wakes up briefly following device reset, then goes back to sleep until activated by the master CPU.
0
1
ENUM
M0P
M0+. Cortex-M0+ is the master CPU.
0
M4
M4. Cortex-M4 is the master CPU.
1
POWERCPU
Identifies the owner of reduced power mode control: which CPU can cause the device to enter Sleep, Deep Sleep, Power-down, and Deep Power-down modes.
6
7
ENUM
M0P
M0+. Cortex-M0+ is the owner of reduced power mode
control.
0
M4
M4. Cortex-M4 is the owner of reduced power mode
control.
1
RESERVED
Reserved. Read value is undefined, only zero should be written..
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written..
1
2
DEVICE_ID0
Part ID register
0x3F8
read-only
n
0x0
0x0
PARTID
Part ID
0
32
DEVICE_ID1
Boot ROM and die revision register
0x3FC
read-only
n
0x0
0x0
REVID
Revision.
0
32
FIFOCTRL
Serial interface FIFO enables
0x148
read-write
n
0x0
0x0
RESERVED
Reserved
6
7
RESERVED
Reserved
7
8
RESERVED
Reserved
7
8
SPI0RXFIFOEN
SPI0 receiver FIFO enable
12
13
SPI0TXFIFOEN
SPI0 transmitter FIFO enable
4
5
SPI1RXFIFOEN
SPI1 receiver FIFO enable
13
14
SPI1TXFIFOEN
SPI1 transmitter FIFO enable
5
6
U0RXFIFOEN
USART0 receiver FIFO enable
8
9
U0TXFIFOEN
USART0 transmitter FIFO enable
0
1
U1RXFIFOEN
USART1 receiver FIFO enable
9
10
U1TXFIFOEN
USART1 transmitter FIFO enable
1
2
U2RXFIFOEN
USART2 receiver FIFO enable
10
11
U2TXFIFOEN
USART2 transmitter FIFO enable
2
3
U3RXFIFOEN
USART3 receiver FIFO enable
11
12
U3TXFIFOEN
USART3 transmitter FIFO enable
3
4
FLASHCFG
Flash wait states configuration
0x124
read-write
n
0x0
0x0
FLASHTIM
Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
12
15
ENUM
1_CLOCK_CYCLE
1 clock cycle. 1 system clock flash access time
(for system clock frequencies of up to MHz).
0x0
2_CLOCK_CYCLES
2 clock cycles. 2 system clocks flash access time
(for system clock frequencies of up to MHz).
0x1
3_CLOCK_CYCLES
3 clock cycles. 3 system clocks flash access time
(for system clock frequencies of up to MHz).
0x2
4_CLOCK_CYCLES
4 clock cycles. 4 system clocks flash access
time.
0x3
5_CLOCK_CYCLES
5 clock cycles. 5 system clocks flash access
time.
0x4
6_CLOCK_CYCLES
6 clock cycles. 6 system clocks flash access
time.
0x5
7_CLOCK_CYCLES
7 clock cycles. 7 system clocks flash access
time.
0x6
8_CLOCK_CYCLES
8 clock cycles. 8 system clocks flash access
time.
0x7
RESERVED
Reserved. Do not change the value of these bits. Bits 11:0 must be written back exactly as read.
0
12
RESERVED
Reserved. Do not change the value of these bits. Bits 11:0 must be written back exactly as read.
0
12
FREQMECTRL
Frequency measure register
0x120
read-write
n
0x0
0x0
CAPVAL
Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only.
0
14
PROG
Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0).
31
32
RESERVED
Reserved. Read value is undefined, only zero should be written.
14
31
IRCCTRL
IRC oscillator control
0x184
read-write
n
0x0
0x0
RESERVED
Reserved
8
32
TRIM
Trim value
0
8
JTAGIDCODE
JTAG ID code register
0x3F4
read-only
n
0x0
0x0
JTAGID
JTAG ID code.
0
32
MAINCLKSELA
Main clock source select A
0x80
read-write
n
0x0
0x0
RESERVED
Reserved
2
32
SEL
Clock source for main clock source selector A
0
2
ENUM
IRC_OSCILLATOR
IRC Oscillator
0x0
CLKIN
CLKIN
0x1
WATCHDOG_OSCILLATOR
Watchdog oscillator
0x2
RESERVED
Reserved
0x3
MAINCLKSELB
Main clock source select B
0x84
read-write
n
0x0
0x0
RESERVED
Reserved
2
32
SEL
Clock source for main clock source selector B. Selects the clock source for the main clock.
0
2
ENUM
MAINCLKSELA
MAINCLKSELA. Use the clock source selected in
MAINCLKSELA register.
0x0
SYSTEM_PLL_INPUT
System PLL input.
0x1
SYSTEM_PLL_OUTPUT
System PLL output.
0x2
RTC_OSC_OUTPUT
RTC osc output. RTC oscillator 32 kHz
output.
0x3
NMISRC
NMI Source Select
0x1C
read-write
n
0x0
0x0
IRQM0
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+, if enabled by NMIENM0.
8
14
IRQM4
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.
0
6
NMIENM0
Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0.
30
31
NMIENM4
Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.
31
32
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
8
PDRUNCFG
Power configuration register
0x210
read-write
n
0x0
0x0
PDEN_32K_OSC
32 kHz RTC oscillator. 0 = Powered; 1 = Powered down.
24
25
PDEN_ADC0
ADC0. 0 = Powered; 1 = Powered down.
10
11
PDEN_BOD_INTR
Brown-out Detect interrupt. 0 = Powered; 1 = Powered down.
8
9
PDEN_BOD_RST
Brown-out Detect reset. 0 = Powered; 1 = Powered down.
7
8
PDEN_FLASH
Flash memory. 0 = Powered; 1 = Powered down.
5
6
PDEN_IRC
IRC oscillator. 0 = Powered; 1 = Powered down.
4
5
PDEN_IRC_OSC
IRC oscillator output. 0 = Powered; 1 = Powered down.
3
4
PDEN_ROM
ROM. 0 = Powered; 1 = Powered down.
17
18
PDEN_SRAM0A
First 8 kB of SRAM0). 0 = Powered; 1 = Powered down.
13
14
PDEN_SRAM0B
Remaining portion of SRAM0). 0 = Powered; 1 = Powered down.
14
15
PDEN_SRAM1
SRAM1. 0 = Powered; 1 = Powered down.
15
16
PDEN_SRAM2
SRAM2 (undedicated 8 kB RAM). 0 = Powered; 1 = Powered down.
16
17
PDEN_SYS_PLL
PLL0. 0 = Powered; 1 = Powered down.
22
23
PDEN_VDDA
Vdda to the ADC, must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down.
19
20
PDEN_VREFP
Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down.
23
24
PDEN_WDT_OSC
Watchdog oscillator. 0 = Powered; 1 = Powered down.
20
21
RESERVED
.
0
3
RESERVED
Reserved.
6
7
RESERVED
Reserved.
9
10
RESERVED
Reserved.
11
13
RESERVED
Reserved.
18
19
RESERVED
Reserved.
21
22
RESERVED
Reserved.
21
22
PDRUNCFGCLR
Clear bits in PDRUNCFG
0x218
write-only
n
0x0
0x0
PD_CLR
Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them.
0
32
PDRUNCFGSET
Set bits in PDRUNCFG
0x214
write-only
n
0x0
0x0
PD_SET
Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them.
0
32
PIOPORCAP0
POR captured PIO status 0
0x5C
read-only
n
0x0
0x0
PIOPORSTAT
State of PIO0_31 through PIO0_0 at power-on reset
0
32
PIOPORCAP1
POR captured PIO status 1
0x60
read-only
n
0x0
0x0
PIOPORSTAT
State of PIO1_31 through PIO1_0 at power-on reset
0
32
PIORESCAP0
Reset captured PIO status 0
0x68
read-only
n
0x0
0x0
PIORESSTAT
State of PIO0_31 through PIO0_0 for resets other than power-on reset.
0
32
PIORESCAP1
Reset captured PIO status 1
0x6C
read-only
n
0x0
0x0
PIORESSTAT
State of PIO1_31 through PIO1_0 for resets other than power-on reset.
0
32
PRESETCTRL0
Peripheral reset control 0
0x44
read-write
n
0x0
0x0
ADC0_RST
ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
27
28
CRC_RST
CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
21
22
DMA_RST
DMA reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
20
21
FLASH_RST
Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
7
8
FMC_RST
Flash accelerator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
8
9
GINT_RST
Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
19
20
GPIO0_RST
GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
14
15
GPIO1_RST
GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
15
16
IOCON_RST
IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
13
14
MAILBOX_RST
Mailbox reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
26
27
MUX_RST
Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
11
12
PINT_RST
Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
18
19
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
12
13
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
18
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
26
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
26
RTC_RST
RTC reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
23
24
WWDT_RST
Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
22
23
PRESETCTRL1
Peripheral reset control 1
0x48
read-write
n
0x0
0x0
FIFO_RST
System FIFO reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
9
10
MRT_RST
Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
11
22
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
26
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
26
RIT_RST
Repetitive interrupt timer (RIT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
1
2
SCT0_RST
State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
2
3
TIMER2_RST
Timer 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
22
23
TIMER3_RST
Timer 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
26
27
TIMER4_RST
Timer 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
27
28
UTICK_RST
Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
10
11
PRESETCTRLCLR0
Clear bits in PRESETCTRL0
0x54
write-only
n
0x0
0x0
RST_CLR0
Writing ones to this register clears the corresponding bit or bits in the PRESETCTRL0 register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only zeroes should be written to them.
0
32
PRESETCTRLCLR1
Clear bits in PRESETCTRL1
0x58
write-only
n
0x0
0x0
RST_CLR1
Writing ones to this register clears the corresponding bit or bits in the PRESETCTRL1 register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL1 are reserved and only zeroes should be written to them.
0
32
PRESETCTRLSET0
Set bits in PRESETCTRL0
0x4C
write-only
n
0x0
0x0
RST_SET0
Writing ones to this register sets the corresponding bit or bits in the PRESETCTRL0 register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL0 are reserved and only zeroes should be written to them.
0
32
PRESETCTRLSET1
Set bits in PRESETCTRL1
0x50
write-only
n
0x0
0x0
RST_SET1
Writing ones to this register sets the corresponding bit or bits in the PRESETCTRL1 register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRL1 are reserved and only zeroes should be written to them.
0
32
RTCOSCCTRL
RTC oscillator 32 kHz output control
0x190
read-write
n
0x0
0x0
EN
RTC 32 kHz clock enable.
0
1
ENUM
DISABLED
Disabled. RTC clock off.
0
ENABLED
Enabled. RTC clock on.
1
RESERVED
Reserved
1
32
STARTERP0
Start logic 0 wake-up enable register
0x240
read-write
n
0x0
0x0
ADC0_SEQA
ADC0 sequence A interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
26
27
ADC0_SEQB
ADC0 sequence B interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
27
28
ADC0_THCMP
ADC0 threshold and error interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
28
29
BOD
BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
1
2
DMA
DMA wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only.
3
4
GINT0
Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
4
5
I2C0
I2C0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
21
22
I2C1
I2C1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
22
23
I2C2
I2C2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
23
24
MAILBOX
Mailbox interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
31
32
MRT
Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only.
10
11
PINT0
GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
5
6
PINT1
GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
6
7
PINT2
GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
7
8
PINT3
GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
8
9
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
3
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
3
RTC
RTC interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
29
30
SCT0
SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
16
17
SPI0
SPI0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
24
25
SPI1
SPI1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
25
26
TIMER0
Timer 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
11
12
TIMER1
Timer 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
12
13
TIMER2
Timer 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
13
14
TIMER3
Timer 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
14
15
TIMER4
Timer 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only.
15
16
USART0
USART0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
17
18
USART1
USART1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
18
19
USART2
USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
19
20
USART3
USART2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Peripheral interrupt.
20
21
UTICK
Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
9
10
WWDT
WWDT interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
0
1
STARTERP1
Start logic 1 wake-up enable register
0x244
read-write
n
0x0
0x0
GINT1
Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
0
1
PINT4
GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
1
2
PINT5
GPIO pin interrupt 5 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
2
3
PINT6
GPIO pin interrupt 6 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
3
4
PINT7
GPIO pin interrupt 7 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written..
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written..
5
8
RIT
Repetitive Interrupt Timer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only.
8
9
STARTERPCLR0
Clear bits in STARTERP0
0x250
write-only
n
0x0
0x0
START_CLR0
Writing ones to this register clears the corresponding bit or bits in the STARTERP0 register, if they are implemented. Bits that do not correspond to defined bits in STARTERP0 are reserved and only zeroes should be written to them.
0
32
STARTERPCLR1
Clear bits in STARTERP1
0x254
write-only
n
0x0
0x0
START_CLR1
Writing ones to this register clears the corresponding bit or bits in the STARTERP1 register, if they are implemented. Bits that do not correspond to defined bits in STARTERP1 are reserved and only zeroes should be written to them.
0
32
STARTERPSET0
Set bits in STARTERP0
0x248
write-only
n
0x0
0x0
START_SET0
Writing ones to this register sets the corresponding bit or bits in the STARTERP0 register, if they are implemented. Bits that do not correspond to defined bits in STARTERP0 are reserved and only zeroes should be written to them.
0
32
STARTERPSET1
Set bits in STARTERP1
0x24C
write-only
n
0x0
0x0
START_SET1
Writing ones to this register sets the corresponding bit or bits in the STARTERP1 register, if they are implemented. Bits that do not correspond to defined bits in STARTERP1 are reserved and only zeroes should be written to them.
0
32
SYSMEMREMAP
System memory remap
0x0
read-write
n
0x0
0x0
MAP
System memory remap. Value 0x3 is reserved.
0
2
ENUM
BOOT_LOADER_MODE
Boot Loader Mode. Interrupt vectors are re-mapped
to Boot ROM.
0x0
USER_RAM_MODE
User RAM Mode. Interrupt vectors are re-mapped to
Static RAM.
0x1
USER_FLASH_MODE
User Flash Mode. Interrupt vectors are not
re-mapped and reside in Flash.
0x2
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
32
SYSPLLCLKSEL
PLL clock source select
0xA0
read-write
n
0x0
0x0
RESERVED
Reserved
2
32
SEL
System PLL clock source
0
2
ENUM
IRC_OSCILLATOR
IRC Oscillator
0x0
CLKIN
CLKIN
0x1
WATCHDOG_OSCILLATOR
Watchdog oscillator
0x2
RTC_32_KHZ_CLOCK
RTC 32 kHz clock
0x3
SYSPLLCTRL
PLL control
0x1B0
read-write
n
0x0
0x0
BANDSEL
PLL filter control. Set this bit to one when the SSGC is disabled or at low frequencies.
18
19
ENUM
SSCG_CONTROL
SSCG control. The PLL filter uses the parameters
derived from the SSCG decoder.
0
MDEC_CONTROL
MDEC control. The PLL filter uses the programmable
fields SELP, SELR, and SELI in this register to control the
filter constants.
1
BYPASS
PLL bypass control
15
16
ENUM
DISABLED
Disabled. PLL CCO is used to create the PLL
output.
0
ENABLED
Enabled. PLL is bypassed, the PLL input clock is
routed directly to the PLL output (default).
1
BYPASSCCODIV2
Bypass feedback clock divide by 2.
16
17
ENUM
DIVIDE_BY_2
Divide by 2. The CCO feedback clock is divided by 2
in addition to the programmed M divide.
0
BYPASS
Bypass. The CCO feedback clock is divided only by
the programmed M divide.
1
DIRECTI
PLL0 direct input enable
19
20
ENUM
DISABLED
Disabled. The PLL input divider (N divider) output
is used to drive the PLL CCO.
0
ENABLED
Enabled. The PLL input divider (N divider) is
bypassed. the PLL input clock is used directly to drive the
PLL CCO.
1
DIRECTO
PLL0 direct output enable
20
21
ENUM
DISABLED
Disabled. The PLL output divider (P divider) is
used to create the PLL output.
0
ENABLED
Enabled. The PLL output divider (P divider) is
bypassed, the PLL CCO output is used as the PLL
output.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
21
32
SELI
Bandwidth select I value
4
10
SELP
Bandwidth select P value
10
15
SELR
Bandwidth select R value
0
4
UPLIMOFF
Enable spread spectrum/fractional mode
17
18
ENUM
NORMAL_MODE
Normal mode.
0
SSGC_MODE
SSGC mode. Spread spectrum/fractional
mode.
1
SYSPLLNDEC
PLL N decoder
0x1B8
read-write
n
0x0
0x0
NDEC
Decoded N-divider coefficient value
0
10
NREQ
NDEC reload request. When a 1 is written to this bit, the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is changed.
10
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
11
32
SYSPLLPDEC
PLL P decoder
0x1BC
read-write
n
0x0
0x0
PDEC
Decoded P-divider coefficient value
0
7
PREQ
PDEC reload request. When a 1 is written to this bit, the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is changed.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
SYSPLLSSCTRL0
PLL spread spectrum control 0
0x1C0
read-write
n
0x0
0x0
MDEC
Decoded M-divider coefficient value
0
17
MREQ
MDEC reload request. When a 1 is written to this bit, the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is changed.
17
18
RESERVED
Reserved. Read value is undefined, only zero should be written.
19
32
SEL_EXT
Select spread spectrum mode.
18
19
ENUM
SPREAD_SPECTRUM_MODE
Spread spectrum mode. Spread spectrum mode
enabled.
0
MDEC_ENABLED
MDEC enabled. Spread spectrum clock generator not
used.
1
SYSPLLSSCTRL1
PLL spread spectrum control 1
0x1C4
read-write
n
0x0
0x0
DITHER
Select modulation frequency.
29
30
ENUM
FIXED
Fixed. Fixed modulation frequency.
0
DITHER
Dither. Randomly dither between two modulation
frequencies.
1
MC
Modulation waveform control 0 = no compensation Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation
26
28
MD
M- divider value with fraction. MD[18:11] : integer portion of the feedback divider value. MD[10:0] : fractional portion of the feedback divider value.
0
19
MDREQ
MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL. This bit is cleared when the load is complete.
19
20
MF
Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm = 3.9 - 7.8 kHz) 0b001 => Nss = 384 (fm = 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm = 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm = 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm = 32.3 - 64.5 kHz) 0b101 => Nss = 32 (fm = 62.5- 125 kHz) 0b110 => Nss = 24 (fm = 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm = 125- 250 kHz)
20
23
MR
Programmable frequency modulation depth deltafmodpk-pk = Fref x k/Fcco = k/MDdec 0 = no spread 0b000 => k = 0 (no spread spectrum) 0b001 => k = 1 0b010 => k = 1.5 0b011 => k = 2 0b100 => k = 3 0b101 => k = 4 0b110 => k = 6 0b111 => k = 8
23
26
PD
Power down.
28
29
ENUM
ENABLED
Enabled. Spread spectrum controller is
enabled
0
DISABLED
Disabled. Spread spectrum controller is
disabled
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
30
32
SYSPLLSTAT
PLL status
0x1B4
read-only
n
0x0
0x0
LOCK
PLL0 lock indicator
0
1
RESERVED
Reserved
1
32
SYSRSTSTAT
System reset status register
0x40
read-write
n
0x0
0x0
BOD
Status of the Brown-out detect reset
3
4
ENUM
NO_BOD_RESET_DETECTE
No BOD reset detected
0
BOD_RESET_DETECTED
BOD reset detected. Writing a one clears this
reset.
1
EXTRST
Status of the external RESET pin. External reset status.
1
2
ENUM
NO_RESET_EVENT_DETEC
No reset event detected.
0
RESET_DETECTED
Reset detected. Writing a one clears this
reset.
1
POR
POR reset status
0
1
ENUM
NO_POR_DETECTED
No POR detected
0
POR_DETECTED
POR detected. Writing a one clears this
reset.
1
RESERVED
Reserved
5
32
SYSRST
Status of the software system reset
4
5
ENUM
NO_SYSTEM_RESET_DETE
No System reset detected
0
SYSTEM_RESET_DETECTE
System reset detected. Writing a one clears this
reset.
1
WDT
Status of the Watchdog reset
2
3
ENUM
NO_WDT_RESET_DETECTE
No WDT reset detected
0
WDT_RESET_DETECTED
WDT reset detected. Writing a one clears this
reset.
1
SYSTCKCAL
System tick counter calibration
0x14
read-write
n
0x0
0x0
CAL
System tick timer calibration value.
0
24
NOREF
Initial value for the Systick timer.
25
26
RESERVED
Reserved.
26
32
SKEW
Initial value for the Systick timer.
24
25
SYSTICKCLKDIV
SYSTICK clock divider
0xE0
read-write
n
0x0
0x0
DIV
SYSTICK clock divider value. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
USART0
USART0
USART0
0x0
0x0
0x1000
registers
n
UART0
17
ADDR
Address register for automatic address matching.
0x2C
read-write
n
0x0
0x0
ADDRESS
8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
0
8
RESERVED
Reserved, the value read from a reserved bit is not defined.
8
32
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
read-write
n
0x0
0x0
AUTOADDR
Automatic Address matching enable.
19
20
ENUM
DISABLED
Disabled. When addressing is enabled by ADDRDET,
address matching is done by software. This provides the
possibility of versatile addressing (e.g. respond to more
than one address).
0
ENABLED
Enabled. When addressing is enabled by ADDRDET,
address matching is done by hardware, using the value in the
ADDR register as the address to match.
1
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
13
ENUM
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge
of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge
of SCLK.
1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
10
ENUM
NO_FLOW_CONTROL
No flow control. The transmitter does not receive
any automatic flow control signal.
0
FLOW_CONTROL_ENABLED
Flow control enabled. The transmitter uses the CTS
input (or RTS output in loopback mode) for flow control
purposes.
1
DATALEN
Selects the data size for the USART.
2
4
ENUM
7_BIT_DATA_LENGTH
7 bit Data length.
0x0
8_BIT_DATA_LENGTH
8 bit Data length.
0x1
9_BIT_DATA_LENGTH
9 bit data length. The 9th bit is commonly used for
addressing in multidrop mode. See the ADDRDET bit in the CTL
register.
0x2
RESERVED
Reserved.
0x3
ENABLE
USART Enable.
0
1
ENUM
DISABLED
Disabled. The USART is disabled and the internal
state machine and counters are reset. While Enable = 0, all
USART interrupts and DMA transfers are disabled. When Enable
is set again, CFG and most other control bits remain
unchanged. For instance, when re-enabled, the USART will
immediately generate a TxRdy interrupt (if enabled in the
INTENSET register) or a DMA transfer request because the
transmitter has been reset and is therefore
available.
0
ENABLED
Enabled. The USART is enabled for
operation.
1
IOMODE
I/O output mode.
16
17
ENUM
STANDARD
Standard. USART output and input operate in
standard fashion.
0
IRDA
IrDA. USART output and input operate in IrDA
mode.
1
LINMODE
LIN break mode enable.
8
9
ENUM
DISABLED
Disabled. Break detect and generate is configured
for normal operation.
0
ENABLED
Enabled. Break detect and generate is configured
for LIN bus operation.
1
LOOP
Selects data loopback mode.
15
16
ENUM
NORMAL_OPERATION
Normal operation.
0
LOOPBACK_MODE
Loopback mode. This provides a mechanism to perform
diagnostic loopback testing for USART data. Serial data from
the transmitter (Un_TXD) is connected internally to serial
input of the receive (Un_RXD). Un_TXD and Un_RTS activity
will also appear on external pins if these functions are
configured to appear on device pins. The receiver RTS signal
is also looped back to CTS and performs flow control if
enabled by CTSEN.
1
MODE32K
Selects standard or 32 kHz clocking mode.
7
8
ENUM
DISABLED
Disabled. USART uses standard
clocking.
0
ENABLED
Enabled. USART uses the 32 kHz clock from the RTC
oscillator as the clock source to the BRG, and uses a
special bit clocking scheme.
1
OEPOL
Output Enable Polarity.
21
22
ENUM
LOW
Low. If selected by OESEL, the output enable is
active low.
0
HIGH
High. If selected by OESEL, the output enable is
active high.
1
OESEL
Output Enable Select.
20
21
ENUM
STANDARD
Standard. The RTS signal is used as the standard
flow control function.
0
RS_485
RS-485. The RTS signal configured to provide an
output enable signal to control an RS-485
transceiver.
1
OETA
Output Enable Turnaround time enable for RS-485 operation.
18
19
ENUM
DISABLED
Disabled. If selected by OESEL, the Output Enable
signal deasserted at the end of the last stop bit of a
transmission.
0
ENABLED
Enabled. If selected by OESEL, the Output Enable
signal remains asserted for one character time after the end
of the last stop bit of a transmission. OE will also remain
asserted if another transmit begins before it is
deasserted.
1
PARITYSEL
Selects what type of parity is used by the USART.
4
6
ENUM
NO_PARITY
No parity.
0x0
RESERVED
Reserved.
0x1
EVEN_PARITY
Even parity. Adds a bit to each character such that
the number of 1s in a transmitted character is even, and the
number of 1s in a received character is expected to be
even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that
the number of 1s in a transmitted character is odd, and the
number of 1s in a received character is expected to be
odd.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
13
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
17
18
RESERVED
Reserved. Read value is undefined, only zero should be written.
17
18
RXPOL
Receive data polarity.
22
23
ENUM
STANDARD
Standard. The RX signal is used as it arrives from
the pin. This means that the RX rest value is 1, start bit
is 0, data is not inverted, and the stop bit is
1.
0
INVERTED
Inverted. The RX signal is inverted before being
used by the USART. This means that the RX rest value is 0,
start bit is 1, data is inverted, and the stop bit is
0.
1
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
7
ENUM
1_STOP_BIT
1 stop bit.
0
2_STOP_BITS
2 stop bits. This setting should only be used for
asynchronous communication.
1
SYNCEN
Selects synchronous or asynchronous operation.
11
12
ENUM
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
1
SYNCMST
Synchronous mode Master select.
14
15
ENUM
SLAVE
Slave. When synchronous mode is enabled, the USART
is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART
is a master.
1
TXPOL
Transmit data polarity.
23
24
ENUM
STANDARD
Standard. The TX signal is sent out without change.
This means that the TX rest value is 1, start bit is 0, data
is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The TX signal is inverted by the USART
before being sent out. This means that the TX rest value is
0, start bit is 1, data is inverted, and the stop bit is
0.
1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
3
ENUM
DISABLED
Disabled. The USART presents all incoming
data.
0
ENABLED
Enabled. The USART receiver ignores incoming data
that does not have the most significant bit of the data
(typically the 9th bit) = 1. When the data MSB bit = 1, the
receiver treats the incoming data normally, generating a
received data interrupt. Software can then check the data to
see if this is an address that should be handled. If it is,
the ADDRDET bit is cleared by software and further incoming
data is handled normally.
1
AUTOBAUD
Autobaud enable.
16
17
ENUM
DISABLED
Disabled. USART is in normal operating
mode.
0
ENABLED
Enabled. USART is in autobaud mode. This bit should
only be set when the USART receiver is idle. The first start
bit of RX is measured and used the update the BRG register
to match the received data rate. AUTOBAUD is cleared once
this process is complete, or if there is an
AERR.
1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
9
ENUM
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK
cycles only when characters are being sent on Un_TXD or to
complete a character that is being received.
0
CONTINUOUS_CLOCK
Continuous clock. SCLK runs continuously in
synchronous mode, allowing characters to be received on
Un_RxD independently from transmission on
Un_TXD).
1
CLRCCONRX
Clear Continuous Clock.
9
10
ENUM
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared
when a complete character has been received. This bit is
cleared at the same time.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
16
TXBRKEN
Break Enable.
1
2
ENUM
NORMAL_OPERATION
Normal operation.
0
CONTINUOUS_BREAK
Continuous break. Continuous break is sent
immediately when this bit is set, and remains until this bit
is cleared. A break may be sent without danger of corrupting
any currently transmitting character if the transmitter is
first disabled (TXDIS in CTL is set) and then waiting for
the transmitter to be disabled (TXDISINT in STAT = 1) before
writing 1 to TXBRKEN.
1
TXDIS
Transmit Disable.
6
7
ENUM
NOT_DISABLED
Not disabled. USART transmitter is not
disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any
character currently being transmitted is complete. This
feature can be used to facilitate software flow
control.
1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
write-only
n
0x0
0x0
ABERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
16
17
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
6
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
12
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
14
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
9
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
16
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
13
TXDISCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
7
TXIDLECLR
Writing 1 clears the corresponding bit in the INTENSET register.
3
4
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
3
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
read-write
n
0x0
0x0
ABERREN
When 1, enables an interrupt when an auto baud error occurs.
16
17
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
6
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
12
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
14
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
9
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISEEN
When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311.
15
16
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
13
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
7
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
3
4
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
3
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
read-only
n
0x0
0x0
ABERRINT
Auto baud Error Interrupt flag.
16
17
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
6
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
12
FRAMERRINT
Framing Error interrupt flag.
13
14
OVERRUNINT
Overrun Error interrupt flag.
8
9
PARITYERRINT
Parity Error interrupt flag.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISEINT
Received Noise interrupt flag.
15
16
RXRDY
Receiver Ready flag.
0
1
START
This bit is set when a start is detected on the receiver input.
12
13
TXDISINT
Transmitter Disabled Interrupt flag.
6
7
TXIDLE
Transmitter Idle status.
3
4
TXRDY
Transmitter Ready flag.
2
3
OSR
Oversample selection register for asynchronous communication.
0x28
read-write
n
0x0
0x0
OSRVAL
Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit.
0
4
RESERVED
Reserved, the value read from a reserved bit is not defined.
4
32
RXDAT
Receiver Data register. Contains the last character received.
0x14
read-only
n
0x0
0x0
modify
DATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
32
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
read-only
n
0x0
0x0
modify
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
15
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RXDATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
RXNOISE
Received Noise flag. See description of the RxNoiseInt bit in Table 311.
15
16
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
read-write
n
0x0
0x0
ABERR
Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.
16
17
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
5
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
6
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
11
12
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
9
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
11
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
2
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
16
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
13
TXDISSTAT
Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
6
7
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
4
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
3
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
read-write
n
0x0
0x0
RESERVED
Reserved. Only zero should be written.
9
32
TXDATA
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
USART1
USART1
USART0
0x0
0x0
0x1000
registers
n
UART1
18
ADDR
Address register for automatic address matching.
0x2C
read-write
n
0x0
0x0
ADDRESS
8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
0
8
RESERVED
Reserved, the value read from a reserved bit is not defined.
8
32
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
read-write
n
0x0
0x0
AUTOADDR
Automatic Address matching enable.
19
20
ENUM
DISABLED
Disabled. When addressing is enabled by ADDRDET,
address matching is done by software. This provides the
possibility of versatile addressing (e.g. respond to more
than one address).
0
ENABLED
Enabled. When addressing is enabled by ADDRDET,
address matching is done by hardware, using the value in the
ADDR register as the address to match.
1
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
13
ENUM
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge
of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge
of SCLK.
1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
10
ENUM
NO_FLOW_CONTROL
No flow control. The transmitter does not receive
any automatic flow control signal.
0
FLOW_CONTROL_ENABLED
Flow control enabled. The transmitter uses the CTS
input (or RTS output in loopback mode) for flow control
purposes.
1
DATALEN
Selects the data size for the USART.
2
4
ENUM
7_BIT_DATA_LENGTH
7 bit Data length.
0x0
8_BIT_DATA_LENGTH
8 bit Data length.
0x1
9_BIT_DATA_LENGTH
9 bit data length. The 9th bit is commonly used for
addressing in multidrop mode. See the ADDRDET bit in the CTL
register.
0x2
RESERVED
Reserved.
0x3
ENABLE
USART Enable.
0
1
ENUM
DISABLED
Disabled. The USART is disabled and the internal
state machine and counters are reset. While Enable = 0, all
USART interrupts and DMA transfers are disabled. When Enable
is set again, CFG and most other control bits remain
unchanged. For instance, when re-enabled, the USART will
immediately generate a TxRdy interrupt (if enabled in the
INTENSET register) or a DMA transfer request because the
transmitter has been reset and is therefore
available.
0
ENABLED
Enabled. The USART is enabled for
operation.
1
IOMODE
I/O output mode.
16
17
ENUM
STANDARD
Standard. USART output and input operate in
standard fashion.
0
IRDA
IrDA. USART output and input operate in IrDA
mode.
1
LINMODE
LIN break mode enable.
8
9
ENUM
DISABLED
Disabled. Break detect and generate is configured
for normal operation.
0
ENABLED
Enabled. Break detect and generate is configured
for LIN bus operation.
1
LOOP
Selects data loopback mode.
15
16
ENUM
NORMAL_OPERATION
Normal operation.
0
LOOPBACK_MODE
Loopback mode. This provides a mechanism to perform
diagnostic loopback testing for USART data. Serial data from
the transmitter (Un_TXD) is connected internally to serial
input of the receive (Un_RXD). Un_TXD and Un_RTS activity
will also appear on external pins if these functions are
configured to appear on device pins. The receiver RTS signal
is also looped back to CTS and performs flow control if
enabled by CTSEN.
1
MODE32K
Selects standard or 32 kHz clocking mode.
7
8
ENUM
DISABLED
Disabled. USART uses standard
clocking.
0
ENABLED
Enabled. USART uses the 32 kHz clock from the RTC
oscillator as the clock source to the BRG, and uses a
special bit clocking scheme.
1
OEPOL
Output Enable Polarity.
21
22
ENUM
LOW
Low. If selected by OESEL, the output enable is
active low.
0
HIGH
High. If selected by OESEL, the output enable is
active high.
1
OESEL
Output Enable Select.
20
21
ENUM
STANDARD
Standard. The RTS signal is used as the standard
flow control function.
0
RS_485
RS-485. The RTS signal configured to provide an
output enable signal to control an RS-485
transceiver.
1
OETA
Output Enable Turnaround time enable for RS-485 operation.
18
19
ENUM
DISABLED
Disabled. If selected by OESEL, the Output Enable
signal deasserted at the end of the last stop bit of a
transmission.
0
ENABLED
Enabled. If selected by OESEL, the Output Enable
signal remains asserted for one character time after the end
of the last stop bit of a transmission. OE will also remain
asserted if another transmit begins before it is
deasserted.
1
PARITYSEL
Selects what type of parity is used by the USART.
4
6
ENUM
NO_PARITY
No parity.
0x0
RESERVED
Reserved.
0x1
EVEN_PARITY
Even parity. Adds a bit to each character such that
the number of 1s in a transmitted character is even, and the
number of 1s in a received character is expected to be
even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that
the number of 1s in a transmitted character is odd, and the
number of 1s in a received character is expected to be
odd.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
13
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
17
18
RESERVED
Reserved. Read value is undefined, only zero should be written.
17
18
RXPOL
Receive data polarity.
22
23
ENUM
STANDARD
Standard. The RX signal is used as it arrives from
the pin. This means that the RX rest value is 1, start bit
is 0, data is not inverted, and the stop bit is
1.
0
INVERTED
Inverted. The RX signal is inverted before being
used by the USART. This means that the RX rest value is 0,
start bit is 1, data is inverted, and the stop bit is
0.
1
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
7
ENUM
1_STOP_BIT
1 stop bit.
0
2_STOP_BITS
2 stop bits. This setting should only be used for
asynchronous communication.
1
SYNCEN
Selects synchronous or asynchronous operation.
11
12
ENUM
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
1
SYNCMST
Synchronous mode Master select.
14
15
ENUM
SLAVE
Slave. When synchronous mode is enabled, the USART
is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART
is a master.
1
TXPOL
Transmit data polarity.
23
24
ENUM
STANDARD
Standard. The TX signal is sent out without change.
This means that the TX rest value is 1, start bit is 0, data
is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The TX signal is inverted by the USART
before being sent out. This means that the TX rest value is
0, start bit is 1, data is inverted, and the stop bit is
0.
1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
3
ENUM
DISABLED
Disabled. The USART presents all incoming
data.
0
ENABLED
Enabled. The USART receiver ignores incoming data
that does not have the most significant bit of the data
(typically the 9th bit) = 1. When the data MSB bit = 1, the
receiver treats the incoming data normally, generating a
received data interrupt. Software can then check the data to
see if this is an address that should be handled. If it is,
the ADDRDET bit is cleared by software and further incoming
data is handled normally.
1
AUTOBAUD
Autobaud enable.
16
17
ENUM
DISABLED
Disabled. USART is in normal operating
mode.
0
ENABLED
Enabled. USART is in autobaud mode. This bit should
only be set when the USART receiver is idle. The first start
bit of RX is measured and used the update the BRG register
to match the received data rate. AUTOBAUD is cleared once
this process is complete, or if there is an
AERR.
1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
9
ENUM
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK
cycles only when characters are being sent on Un_TXD or to
complete a character that is being received.
0
CONTINUOUS_CLOCK
Continuous clock. SCLK runs continuously in
synchronous mode, allowing characters to be received on
Un_RxD independently from transmission on
Un_TXD).
1
CLRCCONRX
Clear Continuous Clock.
9
10
ENUM
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared
when a complete character has been received. This bit is
cleared at the same time.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
16
TXBRKEN
Break Enable.
1
2
ENUM
NORMAL_OPERATION
Normal operation.
0
CONTINUOUS_BREAK
Continuous break. Continuous break is sent
immediately when this bit is set, and remains until this bit
is cleared. A break may be sent without danger of corrupting
any currently transmitting character if the transmitter is
first disabled (TXDIS in CTL is set) and then waiting for
the transmitter to be disabled (TXDISINT in STAT = 1) before
writing 1 to TXBRKEN.
1
TXDIS
Transmit Disable.
6
7
ENUM
NOT_DISABLED
Not disabled. USART transmitter is not
disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any
character currently being transmitted is complete. This
feature can be used to facilitate software flow
control.
1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
write-only
n
0x0
0x0
ABERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
16
17
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
6
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
12
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
14
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
9
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
16
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
13
TXDISCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
7
TXIDLECLR
Writing 1 clears the corresponding bit in the INTENSET register.
3
4
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
3
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
read-write
n
0x0
0x0
ABERREN
When 1, enables an interrupt when an auto baud error occurs.
16
17
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
6
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
12
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
14
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
9
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISEEN
When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311.
15
16
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
13
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
7
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
3
4
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
3
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
read-only
n
0x0
0x0
ABERRINT
Auto baud Error Interrupt flag.
16
17
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
6
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
12
FRAMERRINT
Framing Error interrupt flag.
13
14
OVERRUNINT
Overrun Error interrupt flag.
8
9
PARITYERRINT
Parity Error interrupt flag.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISEINT
Received Noise interrupt flag.
15
16
RXRDY
Receiver Ready flag.
0
1
START
This bit is set when a start is detected on the receiver input.
12
13
TXDISINT
Transmitter Disabled Interrupt flag.
6
7
TXIDLE
Transmitter Idle status.
3
4
TXRDY
Transmitter Ready flag.
2
3
OSR
Oversample selection register for asynchronous communication.
0x28
read-write
n
0x0
0x0
OSRVAL
Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit.
0
4
RESERVED
Reserved, the value read from a reserved bit is not defined.
4
32
RXDAT
Receiver Data register. Contains the last character received.
0x14
read-only
n
0x0
0x0
modify
DATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
32
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
read-only
n
0x0
0x0
modify
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
15
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RXDATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
RXNOISE
Received Noise flag. See description of the RxNoiseInt bit in Table 311.
15
16
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
read-write
n
0x0
0x0
ABERR
Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.
16
17
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
5
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
6
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
11
12
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
9
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
11
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
2
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
16
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
13
TXDISSTAT
Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
6
7
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
4
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
3
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
read-write
n
0x0
0x0
RESERVED
Reserved. Only zero should be written.
9
32
TXDATA
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
USART2
USART2
USART0
0x0
0x0
0x1000
registers
n
UART2
19
ADDR
Address register for automatic address matching.
0x2C
read-write
n
0x0
0x0
ADDRESS
8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
0
8
RESERVED
Reserved, the value read from a reserved bit is not defined.
8
32
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
read-write
n
0x0
0x0
AUTOADDR
Automatic Address matching enable.
19
20
ENUM
DISABLED
Disabled. When addressing is enabled by ADDRDET,
address matching is done by software. This provides the
possibility of versatile addressing (e.g. respond to more
than one address).
0
ENABLED
Enabled. When addressing is enabled by ADDRDET,
address matching is done by hardware, using the value in the
ADDR register as the address to match.
1
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
13
ENUM
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge
of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge
of SCLK.
1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
10
ENUM
NO_FLOW_CONTROL
No flow control. The transmitter does not receive
any automatic flow control signal.
0
FLOW_CONTROL_ENABLED
Flow control enabled. The transmitter uses the CTS
input (or RTS output in loopback mode) for flow control
purposes.
1
DATALEN
Selects the data size for the USART.
2
4
ENUM
7_BIT_DATA_LENGTH
7 bit Data length.
0x0
8_BIT_DATA_LENGTH
8 bit Data length.
0x1
9_BIT_DATA_LENGTH
9 bit data length. The 9th bit is commonly used for
addressing in multidrop mode. See the ADDRDET bit in the CTL
register.
0x2
RESERVED
Reserved.
0x3
ENABLE
USART Enable.
0
1
ENUM
DISABLED
Disabled. The USART is disabled and the internal
state machine and counters are reset. While Enable = 0, all
USART interrupts and DMA transfers are disabled. When Enable
is set again, CFG and most other control bits remain
unchanged. For instance, when re-enabled, the USART will
immediately generate a TxRdy interrupt (if enabled in the
INTENSET register) or a DMA transfer request because the
transmitter has been reset and is therefore
available.
0
ENABLED
Enabled. The USART is enabled for
operation.
1
IOMODE
I/O output mode.
16
17
ENUM
STANDARD
Standard. USART output and input operate in
standard fashion.
0
IRDA
IrDA. USART output and input operate in IrDA
mode.
1
LINMODE
LIN break mode enable.
8
9
ENUM
DISABLED
Disabled. Break detect and generate is configured
for normal operation.
0
ENABLED
Enabled. Break detect and generate is configured
for LIN bus operation.
1
LOOP
Selects data loopback mode.
15
16
ENUM
NORMAL_OPERATION
Normal operation.
0
LOOPBACK_MODE
Loopback mode. This provides a mechanism to perform
diagnostic loopback testing for USART data. Serial data from
the transmitter (Un_TXD) is connected internally to serial
input of the receive (Un_RXD). Un_TXD and Un_RTS activity
will also appear on external pins if these functions are
configured to appear on device pins. The receiver RTS signal
is also looped back to CTS and performs flow control if
enabled by CTSEN.
1
MODE32K
Selects standard or 32 kHz clocking mode.
7
8
ENUM
DISABLED
Disabled. USART uses standard
clocking.
0
ENABLED
Enabled. USART uses the 32 kHz clock from the RTC
oscillator as the clock source to the BRG, and uses a
special bit clocking scheme.
1
OEPOL
Output Enable Polarity.
21
22
ENUM
LOW
Low. If selected by OESEL, the output enable is
active low.
0
HIGH
High. If selected by OESEL, the output enable is
active high.
1
OESEL
Output Enable Select.
20
21
ENUM
STANDARD
Standard. The RTS signal is used as the standard
flow control function.
0
RS_485
RS-485. The RTS signal configured to provide an
output enable signal to control an RS-485
transceiver.
1
OETA
Output Enable Turnaround time enable for RS-485 operation.
18
19
ENUM
DISABLED
Disabled. If selected by OESEL, the Output Enable
signal deasserted at the end of the last stop bit of a
transmission.
0
ENABLED
Enabled. If selected by OESEL, the Output Enable
signal remains asserted for one character time after the end
of the last stop bit of a transmission. OE will also remain
asserted if another transmit begins before it is
deasserted.
1
PARITYSEL
Selects what type of parity is used by the USART.
4
6
ENUM
NO_PARITY
No parity.
0x0
RESERVED
Reserved.
0x1
EVEN_PARITY
Even parity. Adds a bit to each character such that
the number of 1s in a transmitted character is even, and the
number of 1s in a received character is expected to be
even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that
the number of 1s in a transmitted character is odd, and the
number of 1s in a received character is expected to be
odd.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
13
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
17
18
RESERVED
Reserved. Read value is undefined, only zero should be written.
17
18
RXPOL
Receive data polarity.
22
23
ENUM
STANDARD
Standard. The RX signal is used as it arrives from
the pin. This means that the RX rest value is 1, start bit
is 0, data is not inverted, and the stop bit is
1.
0
INVERTED
Inverted. The RX signal is inverted before being
used by the USART. This means that the RX rest value is 0,
start bit is 1, data is inverted, and the stop bit is
0.
1
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
7
ENUM
1_STOP_BIT
1 stop bit.
0
2_STOP_BITS
2 stop bits. This setting should only be used for
asynchronous communication.
1
SYNCEN
Selects synchronous or asynchronous operation.
11
12
ENUM
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
1
SYNCMST
Synchronous mode Master select.
14
15
ENUM
SLAVE
Slave. When synchronous mode is enabled, the USART
is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART
is a master.
1
TXPOL
Transmit data polarity.
23
24
ENUM
STANDARD
Standard. The TX signal is sent out without change.
This means that the TX rest value is 1, start bit is 0, data
is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The TX signal is inverted by the USART
before being sent out. This means that the TX rest value is
0, start bit is 1, data is inverted, and the stop bit is
0.
1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
3
ENUM
DISABLED
Disabled. The USART presents all incoming
data.
0
ENABLED
Enabled. The USART receiver ignores incoming data
that does not have the most significant bit of the data
(typically the 9th bit) = 1. When the data MSB bit = 1, the
receiver treats the incoming data normally, generating a
received data interrupt. Software can then check the data to
see if this is an address that should be handled. If it is,
the ADDRDET bit is cleared by software and further incoming
data is handled normally.
1
AUTOBAUD
Autobaud enable.
16
17
ENUM
DISABLED
Disabled. USART is in normal operating
mode.
0
ENABLED
Enabled. USART is in autobaud mode. This bit should
only be set when the USART receiver is idle. The first start
bit of RX is measured and used the update the BRG register
to match the received data rate. AUTOBAUD is cleared once
this process is complete, or if there is an
AERR.
1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
9
ENUM
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK
cycles only when characters are being sent on Un_TXD or to
complete a character that is being received.
0
CONTINUOUS_CLOCK
Continuous clock. SCLK runs continuously in
synchronous mode, allowing characters to be received on
Un_RxD independently from transmission on
Un_TXD).
1
CLRCCONRX
Clear Continuous Clock.
9
10
ENUM
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared
when a complete character has been received. This bit is
cleared at the same time.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
16
TXBRKEN
Break Enable.
1
2
ENUM
NORMAL_OPERATION
Normal operation.
0
CONTINUOUS_BREAK
Continuous break. Continuous break is sent
immediately when this bit is set, and remains until this bit
is cleared. A break may be sent without danger of corrupting
any currently transmitting character if the transmitter is
first disabled (TXDIS in CTL is set) and then waiting for
the transmitter to be disabled (TXDISINT in STAT = 1) before
writing 1 to TXBRKEN.
1
TXDIS
Transmit Disable.
6
7
ENUM
NOT_DISABLED
Not disabled. USART transmitter is not
disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any
character currently being transmitted is complete. This
feature can be used to facilitate software flow
control.
1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
write-only
n
0x0
0x0
ABERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
16
17
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
6
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
12
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
14
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
9
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
16
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
13
TXDISCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
7
TXIDLECLR
Writing 1 clears the corresponding bit in the INTENSET register.
3
4
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
3
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
read-write
n
0x0
0x0
ABERREN
When 1, enables an interrupt when an auto baud error occurs.
16
17
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
6
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
12
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
14
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
9
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISEEN
When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311.
15
16
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
13
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
7
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
3
4
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
3
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
read-only
n
0x0
0x0
ABERRINT
Auto baud Error Interrupt flag.
16
17
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
6
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
12
FRAMERRINT
Framing Error interrupt flag.
13
14
OVERRUNINT
Overrun Error interrupt flag.
8
9
PARITYERRINT
Parity Error interrupt flag.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISEINT
Received Noise interrupt flag.
15
16
RXRDY
Receiver Ready flag.
0
1
START
This bit is set when a start is detected on the receiver input.
12
13
TXDISINT
Transmitter Disabled Interrupt flag.
6
7
TXIDLE
Transmitter Idle status.
3
4
TXRDY
Transmitter Ready flag.
2
3
OSR
Oversample selection register for asynchronous communication.
0x28
read-write
n
0x0
0x0
OSRVAL
Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit.
0
4
RESERVED
Reserved, the value read from a reserved bit is not defined.
4
32
RXDAT
Receiver Data register. Contains the last character received.
0x14
read-only
n
0x0
0x0
modify
DATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
32
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
read-only
n
0x0
0x0
modify
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
15
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RXDATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
RXNOISE
Received Noise flag. See description of the RxNoiseInt bit in Table 311.
15
16
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
read-write
n
0x0
0x0
ABERR
Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.
16
17
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
5
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
6
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
11
12
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
9
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
11
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
2
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
16
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
13
TXDISSTAT
Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
6
7
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
4
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
3
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
read-write
n
0x0
0x0
RESERVED
Reserved. Only zero should be written.
9
32
TXDATA
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
USART3
USART3
USART0
0x0
0x0
0x1000
registers
n
UART3
20
ADDR
Address register for automatic address matching.
0x2C
read-write
n
0x0
0x0
ADDRESS
8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
0
8
RESERVED
Reserved, the value read from a reserved bit is not defined.
8
32
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.
0
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
read-write
n
0x0
0x0
AUTOADDR
Automatic Address matching enable.
19
20
ENUM
DISABLED
Disabled. When addressing is enabled by ADDRDET,
address matching is done by software. This provides the
possibility of versatile addressing (e.g. respond to more
than one address).
0
ENABLED
Enabled. When addressing is enabled by ADDRDET,
address matching is done by hardware, using the value in the
ADDR register as the address to match.
1
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
13
ENUM
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge
of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge
of SCLK.
1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
10
ENUM
NO_FLOW_CONTROL
No flow control. The transmitter does not receive
any automatic flow control signal.
0
FLOW_CONTROL_ENABLED
Flow control enabled. The transmitter uses the CTS
input (or RTS output in loopback mode) for flow control
purposes.
1
DATALEN
Selects the data size for the USART.
2
4
ENUM
7_BIT_DATA_LENGTH
7 bit Data length.
0x0
8_BIT_DATA_LENGTH
8 bit Data length.
0x1
9_BIT_DATA_LENGTH
9 bit data length. The 9th bit is commonly used for
addressing in multidrop mode. See the ADDRDET bit in the CTL
register.
0x2
RESERVED
Reserved.
0x3
ENABLE
USART Enable.
0
1
ENUM
DISABLED
Disabled. The USART is disabled and the internal
state machine and counters are reset. While Enable = 0, all
USART interrupts and DMA transfers are disabled. When Enable
is set again, CFG and most other control bits remain
unchanged. For instance, when re-enabled, the USART will
immediately generate a TxRdy interrupt (if enabled in the
INTENSET register) or a DMA transfer request because the
transmitter has been reset and is therefore
available.
0
ENABLED
Enabled. The USART is enabled for
operation.
1
IOMODE
I/O output mode.
16
17
ENUM
STANDARD
Standard. USART output and input operate in
standard fashion.
0
IRDA
IrDA. USART output and input operate in IrDA
mode.
1
LINMODE
LIN break mode enable.
8
9
ENUM
DISABLED
Disabled. Break detect and generate is configured
for normal operation.
0
ENABLED
Enabled. Break detect and generate is configured
for LIN bus operation.
1
LOOP
Selects data loopback mode.
15
16
ENUM
NORMAL_OPERATION
Normal operation.
0
LOOPBACK_MODE
Loopback mode. This provides a mechanism to perform
diagnostic loopback testing for USART data. Serial data from
the transmitter (Un_TXD) is connected internally to serial
input of the receive (Un_RXD). Un_TXD and Un_RTS activity
will also appear on external pins if these functions are
configured to appear on device pins. The receiver RTS signal
is also looped back to CTS and performs flow control if
enabled by CTSEN.
1
MODE32K
Selects standard or 32 kHz clocking mode.
7
8
ENUM
DISABLED
Disabled. USART uses standard
clocking.
0
ENABLED
Enabled. USART uses the 32 kHz clock from the RTC
oscillator as the clock source to the BRG, and uses a
special bit clocking scheme.
1
OEPOL
Output Enable Polarity.
21
22
ENUM
LOW
Low. If selected by OESEL, the output enable is
active low.
0
HIGH
High. If selected by OESEL, the output enable is
active high.
1
OESEL
Output Enable Select.
20
21
ENUM
STANDARD
Standard. The RTS signal is used as the standard
flow control function.
0
RS_485
RS-485. The RTS signal configured to provide an
output enable signal to control an RS-485
transceiver.
1
OETA
Output Enable Turnaround time enable for RS-485 operation.
18
19
ENUM
DISABLED
Disabled. If selected by OESEL, the Output Enable
signal deasserted at the end of the last stop bit of a
transmission.
0
ENABLED
Enabled. If selected by OESEL, the Output Enable
signal remains asserted for one character time after the end
of the last stop bit of a transmission. OE will also remain
asserted if another transmit begins before it is
deasserted.
1
PARITYSEL
Selects what type of parity is used by the USART.
4
6
ENUM
NO_PARITY
No parity.
0x0
RESERVED
Reserved.
0x1
EVEN_PARITY
Even parity. Adds a bit to each character such that
the number of 1s in a transmitted character is even, and the
number of 1s in a received character is expected to be
even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that
the number of 1s in a transmitted character is odd, and the
number of 1s in a received character is expected to be
odd.
0x3
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
13
14
RESERVED
Reserved. Read value is undefined, only zero should be written.
17
18
RESERVED
Reserved. Read value is undefined, only zero should be written.
17
18
RXPOL
Receive data polarity.
22
23
ENUM
STANDARD
Standard. The RX signal is used as it arrives from
the pin. This means that the RX rest value is 1, start bit
is 0, data is not inverted, and the stop bit is
1.
0
INVERTED
Inverted. The RX signal is inverted before being
used by the USART. This means that the RX rest value is 0,
start bit is 1, data is inverted, and the stop bit is
0.
1
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
7
ENUM
1_STOP_BIT
1 stop bit.
0
2_STOP_BITS
2 stop bits. This setting should only be used for
asynchronous communication.
1
SYNCEN
Selects synchronous or asynchronous operation.
11
12
ENUM
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
1
SYNCMST
Synchronous mode Master select.
14
15
ENUM
SLAVE
Slave. When synchronous mode is enabled, the USART
is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART
is a master.
1
TXPOL
Transmit data polarity.
23
24
ENUM
STANDARD
Standard. The TX signal is sent out without change.
This means that the TX rest value is 1, start bit is 0, data
is not inverted, and the stop bit is 1.
0
INVERTED
Inverted. The TX signal is inverted by the USART
before being sent out. This means that the TX rest value is
0, start bit is 1, data is inverted, and the stop bit is
0.
1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
3
ENUM
DISABLED
Disabled. The USART presents all incoming
data.
0
ENABLED
Enabled. The USART receiver ignores incoming data
that does not have the most significant bit of the data
(typically the 9th bit) = 1. When the data MSB bit = 1, the
receiver treats the incoming data normally, generating a
received data interrupt. Software can then check the data to
see if this is an address that should be handled. If it is,
the ADDRDET bit is cleared by software and further incoming
data is handled normally.
1
AUTOBAUD
Autobaud enable.
16
17
ENUM
DISABLED
Disabled. USART is in normal operating
mode.
0
ENABLED
Enabled. USART is in autobaud mode. This bit should
only be set when the USART receiver is idle. The first start
bit of RX is measured and used the update the BRG register
to match the received data rate. AUTOBAUD is cleared once
this process is complete, or if there is an
AERR.
1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
9
ENUM
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK
cycles only when characters are being sent on Un_TXD or to
complete a character that is being received.
0
CONTINUOUS_CLOCK
Continuous clock. SCLK runs continuously in
synchronous mode, allowing characters to be received on
Un_RxD independently from transmission on
Un_TXD).
1
CLRCCONRX
Clear Continuous Clock.
9
10
ENUM
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared
when a complete character has been received. This bit is
cleared at the same time.
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
1
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
10
16
TXBRKEN
Break Enable.
1
2
ENUM
NORMAL_OPERATION
Normal operation.
0
CONTINUOUS_BREAK
Continuous break. Continuous break is sent
immediately when this bit is set, and remains until this bit
is cleared. A break may be sent without danger of corrupting
any currently transmitting character if the transmitter is
first disabled (TXDIS in CTL is set) and then waiting for
the transmitter to be disabled (TXDISINT in STAT = 1) before
writing 1 to TXBRKEN.
1
TXDIS
Transmit Disable.
6
7
ENUM
NOT_DISABLED
Not disabled. USART transmitter is not
disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any
character currently being transmitted is complete. This
feature can be used to facilitate software flow
control.
1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
write-only
n
0x0
0x0
ABERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
16
17
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
6
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
12
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
14
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
9
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
16
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
13
TXDISCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
7
TXIDLECLR
Writing 1 clears the corresponding bit in the INTENSET register.
3
4
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
3
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
read-write
n
0x0
0x0
ABERREN
When 1, enables an interrupt when an auto baud error occurs.
16
17
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
6
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
12
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
14
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
9
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISEEN
When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 311.
15
16
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
13
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
7
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
3
4
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
3
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
read-only
n
0x0
0x0
ABERRINT
Auto baud Error Interrupt flag.
16
17
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
6
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
12
FRAMERRINT
Framing Error interrupt flag.
13
14
OVERRUNINT
Overrun Error interrupt flag.
8
9
PARITYERRINT
Parity Error interrupt flag.
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
1
2
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
5
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
11
RXNOISEINT
Received Noise interrupt flag.
15
16
RXRDY
Receiver Ready flag.
0
1
START
This bit is set when a start is detected on the receiver input.
12
13
TXDISINT
Transmitter Disabled Interrupt flag.
6
7
TXIDLE
Transmitter Idle status.
3
4
TXRDY
Transmitter Ready flag.
2
3
OSR
Oversample selection register for asynchronous communication.
0x28
read-write
n
0x0
0x0
OSRVAL
Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit.
0
4
RESERVED
Reserved, the value read from a reserved bit is not defined.
4
32
RXDAT
Receiver Data register. Contains the last character received.
0x14
read-only
n
0x0
0x0
modify
DATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
32
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
read-only
n
0x0
0x0
modify
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
15
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RXDATA
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
RXNOISE
Received Noise flag. See description of the RxNoiseInt bit in Table 311.
15
16
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
read-write
n
0x0
0x0
ABERR
Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.
16
17
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
5
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
6
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
11
12
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
9
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..
14
15
RESERVED
Reserved. Read value is undefined, only zero should be written.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RESERVED
Reserved. Read value is undefined, only zero should be written.
9
10
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
11
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
2
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
16
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
13
TXDISSTAT
Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
6
7
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
4
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
3
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
read-write
n
0x0
0x0
RESERVED
Reserved. Only zero should be written.
9
32
TXDATA
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
UTICK
Micro-tick timer
UTICK
0x0
0x0
0x1000
registers
n
UTICK
9
CTRL
Control register.
0x0
read-write
n
0x0
0x0
DELAYVAL
Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.
0
31
REPEAT
Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.
31
32
STAT
Status register.
0x4
read-write
n
0x0
0x0
ACTIVE
Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.
1
2
INTR
Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag.
0
1
RESERVED
Reserved
2
32
VFIFO
System FIFO for Serial Peripherals
VFIFO
0x0
0x0
0x50
registers
n
CFGSPI0
SPI0 configuration
0x4000
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RXTHRESHOLD
Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example, when RxThreshold = 0, the threshold is exceeded when there is at least one entry in the receive FIFO. An interrupt can be generated when the RxThreshold has been reached, but has no effect on DMA requests, which are generated whenever the receiver FIFO is not empty.
16
24
TIMEOUTBASE
Specifies the least significant timer bit to compare to TimeoutValue. Value can be 0 through 15.
8
12
TIMEOUTCONTONEMPTY
Timeout Continue On Empty. When 0, the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1, the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the timeout to be used to flag idle peripherals, and could potentially be used to indicate the end of a transmission of indeterminate length.
5
6
TIMEOUTCONTONWRITE
Timeout Continue On Write. When 0, the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1, the timeout for the related peripheral is not reset every time data is transferred into the receive FIFO. This allows the timeout to be applied to accumulated data, perhaps related to the FIFO threshold.
4
5
TIMEOUTVALUE
Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. TimeoutValue should not be 0 or 1 when timeout is enabled.
12
16
TXTHRESHOLD
Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example, when TxThreshold = 0, the threshold is exceeded when there is at least one free entry in the transmit FIFO. An interrupt can be generated when the TxThreshold has been reached, but has no effect on DMA requests, which are generated whenever the transmit FIFO has any free entries.
24
32
CFGSPI1
SPI0 configuration
0x6100
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RXTHRESHOLD
Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example, when RxThreshold = 0, the threshold is exceeded when there is at least one entry in the receive FIFO. An interrupt can be generated when the RxThreshold has been reached, but has no effect on DMA requests, which are generated whenever the receiver FIFO is not empty.
16
24
TIMEOUTBASE
Specifies the least significant timer bit to compare to TimeoutValue. Value can be 0 through 15.
8
12
TIMEOUTCONTONEMPTY
Timeout Continue On Empty. When 0, the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1, the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the timeout to be used to flag idle peripherals, and could potentially be used to indicate the end of a transmission of indeterminate length.
5
6
TIMEOUTCONTONWRITE
Timeout Continue On Write. When 0, the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1, the timeout for the related peripheral is not reset every time data is transferred into the receive FIFO. This allows the timeout to be applied to accumulated data, perhaps related to the FIFO threshold.
4
5
TIMEOUTVALUE
Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. TimeoutValue should not be 0 or 1 when timeout is enabled.
12
16
TXTHRESHOLD
Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example, when TxThreshold = 0, the threshold is exceeded when there is at least one free entry in the transmit FIFO. An interrupt can be generated when the TxThreshold has been reached, but has no effect on DMA requests, which are generated whenever the transmit FIFO has any free entries.
24
32
CFGUSART0
USART0 configuration
0x2000
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RXTHRESHOLD
Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example, when RxThreshold = 0, the threshold is exceeded when there is at least one entry in the receive FIFO. An interrupt can be generated when the RxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the receiver FIFO is not empty.
16
24
TIMEOUTBASE
Specifies the least significant timer bit to compare to TimeoutValue. See Section 24.5.7.1 below. Value can be 0 through 15.
8
12
TIMEOUTCONTONEMPTY
Timeout Continue On Empty. When 0, the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1, the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the timeout to be used to flag idle peripherals, and could potentially be used to indicate the end of a transmission of indeterminate length.
5
6
TIMEOUTCONTONWRITE
Timeout Continue On Write. When 0, the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1, the timeout for the related peripheral is not reset every time data is transferred into the receive FIFO. This allows the timeout to be applied to accumulated data, perhaps related to the FIFO threshold.
4
5
TIMEOUTVALUE
Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. is See Section 24.5.7.1 below. TimeoutValue should not be 0 or 1 when timeout is enabled.
12
16
TXTHRESHOLD
Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example, when TxThreshold = 0, the threshold is exceeded when there is at least one free entry in the transmit FIFO. An interrupt can be generated when the TxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the transmit FIFO has any free entries.
24
32
CFGUSART1
USART0 configuration
0x3100
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RXTHRESHOLD
Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example, when RxThreshold = 0, the threshold is exceeded when there is at least one entry in the receive FIFO. An interrupt can be generated when the RxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the receiver FIFO is not empty.
16
24
TIMEOUTBASE
Specifies the least significant timer bit to compare to TimeoutValue. See Section 24.5.7.1 below. Value can be 0 through 15.
8
12
TIMEOUTCONTONEMPTY
Timeout Continue On Empty. When 0, the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1, the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the timeout to be used to flag idle peripherals, and could potentially be used to indicate the end of a transmission of indeterminate length.
5
6
TIMEOUTCONTONWRITE
Timeout Continue On Write. When 0, the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1, the timeout for the related peripheral is not reset every time data is transferred into the receive FIFO. This allows the timeout to be applied to accumulated data, perhaps related to the FIFO threshold.
4
5
TIMEOUTVALUE
Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. is See Section 24.5.7.1 below. TimeoutValue should not be 0 or 1 when timeout is enabled.
12
16
TXTHRESHOLD
Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example, when TxThreshold = 0, the threshold is exceeded when there is at least one free entry in the transmit FIFO. An interrupt can be generated when the TxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the transmit FIFO has any free entries.
24
32
CFGUSART2
USART0 configuration
0x4300
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RXTHRESHOLD
Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example, when RxThreshold = 0, the threshold is exceeded when there is at least one entry in the receive FIFO. An interrupt can be generated when the RxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the receiver FIFO is not empty.
16
24
TIMEOUTBASE
Specifies the least significant timer bit to compare to TimeoutValue. See Section 24.5.7.1 below. Value can be 0 through 15.
8
12
TIMEOUTCONTONEMPTY
Timeout Continue On Empty. When 0, the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1, the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the timeout to be used to flag idle peripherals, and could potentially be used to indicate the end of a transmission of indeterminate length.
5
6
TIMEOUTCONTONWRITE
Timeout Continue On Write. When 0, the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1, the timeout for the related peripheral is not reset every time data is transferred into the receive FIFO. This allows the timeout to be applied to accumulated data, perhaps related to the FIFO threshold.
4
5
TIMEOUTVALUE
Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. is See Section 24.5.7.1 below. TimeoutValue should not be 0 or 1 when timeout is enabled.
12
16
TXTHRESHOLD
Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example, when TxThreshold = 0, the threshold is exceeded when there is at least one free entry in the transmit FIFO. An interrupt can be generated when the TxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the transmit FIFO has any free entries.
24
32
CFGUSART3
USART0 configuration
0x5600
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
0
4
RXTHRESHOLD
Receive FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of entries in the receive FIFO is greater than this value. For example, when RxThreshold = 0, the threshold is exceeded when there is at least one entry in the receive FIFO. An interrupt can be generated when the RxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the receiver FIFO is not empty.
16
24
TIMEOUTBASE
Specifies the least significant timer bit to compare to TimeoutValue. See Section 24.5.7.1 below. Value can be 0 through 15.
8
12
TIMEOUTCONTONEMPTY
Timeout Continue On Empty. When 0, the timeout for the related peripheral is reset when the receive FIFO becomes empty. When 1, the timeout for the related peripheral is not reset when the receive FIFO becomes empty. This allows the timeout to be used to flag idle peripherals, and could potentially be used to indicate the end of a transmission of indeterminate length.
5
6
TIMEOUTCONTONWRITE
Timeout Continue On Write. When 0, the timeout for the related peripheral is reset every time data is transferred from the peripheral into the receive FIFO. When 1, the timeout for the related peripheral is not reset every time data is transferred into the receive FIFO. This allows the timeout to be applied to accumulated data, perhaps related to the FIFO threshold.
4
5
TIMEOUTVALUE
Specifies the maximum time value for timeout at the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1. is See Section 24.5.7.1 below. TimeoutValue should not be 0 or 1 when timeout is enabled.
12
16
TXTHRESHOLD
Transmit FIFO Threshold. The System FIFO indicates that the threshold has been reached when the number of free entries in the transmit FIFO is less than or equal to this value. For example, when TxThreshold = 0, the threshold is exceeded when there is at least one free entry in the transmit FIFO. An interrupt can be generated when the TxThreshold has been reached (see Section 24.5.10), but has no effect on DMA requests, which are generated whenever the transmit FIFO has any free entries.
24
32
CTLCLRSPI0
SPI0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
0x4020
write-only
n
0x0
0x0
RESERVED
Writing ones to this register clears the corresponding bit or bits in the CTLSETSPI register, if they are implemented. Bits that do not correspond to defined bits in CTLSETSPI are reserved and only zeroes should be written to them.
0
32
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSHCLR
Receive FIFO flush clear. do the clear bits 8 and 9 do anything?
8
9
RXTHINTCLR
Receive FIFO Threshold Interrupt clear.
0
1
RXTIMEOUTINTCLR
Receive FIFO Timeout Interrupt clear.
4
5
TXFLUSHCLR
Transmit FIFO flush clear.
9
10
TXTHINTCLR
Transmit FIFO Threshold Interrupt clear.
1
2
CTLCLRSPI1
SPI0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
0x6130
write-only
n
0x0
0x0
RESERVED
Writing ones to this register clears the corresponding bit or bits in the CTLSETSPI register, if they are implemented. Bits that do not correspond to defined bits in CTLSETSPI are reserved and only zeroes should be written to them.
0
32
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSHCLR
Receive FIFO flush clear. do the clear bits 8 and 9 do anything?
8
9
RXTHINTCLR
Receive FIFO Threshold Interrupt clear.
0
1
RXTIMEOUTINTCLR
Receive FIFO Timeout Interrupt clear.
4
5
TXFLUSHCLR
Transmit FIFO flush clear.
9
10
TXTHINTCLR
Transmit FIFO Threshold Interrupt clear.
1
2
CTLCLRUSART0
USART0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
0x2020
write-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSHCLR
Receive FIFO flush clear.
8
9
RXTHINTCLR
Receive FIFO Threshold Interrupt clear.
0
1
RXTIMEOUTINTCLR
Receive FIFO Time-out Interrupt clear.
4
5
TXFLUSHCLR
Transmit FIFO flush clear.
9
10
TXTHINTCLR
Transmit FIFO Threshold Interrupt clear.
1
2
CTLCLRUSART1
USART0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
0x3130
write-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSHCLR
Receive FIFO flush clear.
8
9
RXTHINTCLR
Receive FIFO Threshold Interrupt clear.
0
1
RXTIMEOUTINTCLR
Receive FIFO Time-out Interrupt clear.
4
5
TXFLUSHCLR
Transmit FIFO flush clear.
9
10
TXTHINTCLR
Transmit FIFO Threshold Interrupt clear.
1
2
CTLCLRUSART2
USART0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
0x4340
write-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSHCLR
Receive FIFO flush clear.
8
9
RXTHINTCLR
Receive FIFO Threshold Interrupt clear.
0
1
RXTIMEOUTINTCLR
Receive FIFO Time-out Interrupt clear.
4
5
TXFLUSHCLR
Transmit FIFO flush clear.
9
10
TXTHINTCLR
Transmit FIFO Threshold Interrupt clear.
1
2
CTLCLRUSART3
USART0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
0x5650
write-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSHCLR
Receive FIFO flush clear.
8
9
RXTHINTCLR
Receive FIFO Threshold Interrupt clear.
0
1
RXTIMEOUTINTCLR
Receive FIFO Time-out Interrupt clear.
4
5
TXFLUSHCLR
Transmit FIFO flush clear.
9
10
TXTHINTCLR
Transmit FIFO Threshold Interrupt clear.
1
2
CTLSETSPI0
SPI0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x4018
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSH
Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
8
9
RXTHINTEN
Receive FIFO Threshold Interrupt Enable.
0
1
RXTIMEOUTINTEN
Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this SPI. Writing a 1 to this bit resets the SPI timeout logic.
4
5
TXFLUSH
Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty.
9
10
TXTHINTEN
Transmit FIFO Threshold Interrupt Enable.
1
2
CTLSETSPI1
SPI0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x6124
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSH
Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
8
9
RXTHINTEN
Receive FIFO Threshold Interrupt Enable.
0
1
RXTIMEOUTINTEN
Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this SPI. Writing a 1 to this bit resets the SPI timeout logic.
4
5
TXFLUSH
Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty.
9
10
TXTHINTEN
Transmit FIFO Threshold Interrupt Enable.
1
2
CTLSETUSART0
USART0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x2018
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSH
Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
8
9
RXTHINTEN
Receive FIFO Threshold Interrupt Enable.
0
1
RXTIMEOUTINTEN
Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this USART. Writing a 1 to this bit resets the USART timeout logic.
4
5
TXFLUSH
Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty.
9
10
TXTHINTEN
Transmit FIFO Threshold Interrupt Enable.
1
2
CTLSETUSART1
USART0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x3124
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSH
Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
8
9
RXTHINTEN
Receive FIFO Threshold Interrupt Enable.
0
1
RXTIMEOUTINTEN
Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this USART. Writing a 1 to this bit resets the USART timeout logic.
4
5
TXFLUSH
Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty.
9
10
TXTHINTEN
Transmit FIFO Threshold Interrupt Enable.
1
2
CTLSETUSART2
USART0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x4330
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSH
Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
8
9
RXTHINTEN
Receive FIFO Threshold Interrupt Enable.
0
1
RXTIMEOUTINTEN
Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this USART. Writing a 1 to this bit resets the USART timeout logic.
4
5
TXFLUSH
Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty.
9
10
TXTHINTEN
Transmit FIFO Threshold Interrupt Enable.
1
2
CTLSETUSART3
USART0 control read and set register. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x563C
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
8
RXFLUSH
Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
8
9
RXTHINTEN
Receive FIFO Threshold Interrupt Enable.
0
1
RXTIMEOUTINTEN
Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the timeout for this USART. Writing a 1 to this bit resets the USART timeout logic.
4
5
TXFLUSH
Transmit FIFO flush. Writing a 1 to this bit forces the transmit FIFO to be empty.
9
10
TXTHINTEN
Transmit FIFO Threshold Interrupt Enable.
1
2
FIFOCFGSPI0
FIFO configuration register for SPI0
0x420
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RXSIZE
Configures the SPI receive FIFO size. A zero values provides no System FIFO service for the related SPI receiver.
0
8
TXSIZE
Configures the SPI transmit FIFO size. A zero values provides no System FIFO service for the related SPI transmitter.
8
16
FIFOCFGSPI1
FIFO configuration register for SPI0
0x634
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RXSIZE
Configures the SPI receive FIFO size. A zero values provides no System FIFO service for the related SPI receiver.
0
8
TXSIZE
Configures the SPI transmit FIFO size. A zero values provides no System FIFO service for the related SPI transmitter.
8
16
FIFOCFGUSART0
FIFO configuration register for USART0
0x220
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RXSIZE
Configures the USART receive FIFO size. A zero values provides no System FIFO service for the related USART receiver.
0
8
TXSIZE
Configures the USART transmit FIFO size. A zero values provides no System FIFO service for the related USART transmitter.
8
16
FIFOCFGUSART1
FIFO configuration register for USART0
0x334
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RXSIZE
Configures the USART receive FIFO size. A zero values provides no System FIFO service for the related USART receiver.
0
8
TXSIZE
Configures the USART transmit FIFO size. A zero values provides no System FIFO service for the related USART transmitter.
8
16
FIFOCFGUSART2
FIFO configuration register for USART0
0x44C
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RXSIZE
Configures the USART receive FIFO size. A zero values provides no System FIFO service for the related USART receiver.
0
8
TXSIZE
Configures the USART transmit FIFO size. A zero values provides no System FIFO service for the related USART transmitter.
8
16
FIFOCFGUSART3
FIFO configuration register for USART0
0x568
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
16
32
RXSIZE
Configures the USART receive FIFO size. A zero values provides no System FIFO service for the related USART receiver.
0
8
TXSIZE
Configures the USART transmit FIFO size. A zero values provides no System FIFO service for the related USART transmitter.
8
16
FIFOCTLSPI
SPI FIFO global control register. These registers are byte, halfword, and word addressable. The upper 16 bits of these registers provide information about the System FIFO configuration, and are specific to each device type.
0x200
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
8
RXEMPTY
All SPI receive FIFOs are empty.
2
3
RXFIFOTOTAL
Reports the receive FIFO space available for SPIs on the System FIFO. The reset value is device specific.
16
24
RXPAUSE
Pause all SPIs receive FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI receivers.
0
1
RXPAUSED
All SPI receive FIFOs are paused.
1
2
TXEMPTY
All SPI transmit FIFOs are empty.
10
11
TXFIFOTOTAL
Reports the transmit FIFO space available for SPIs on the System FIFO. The reset value is device specific.
24
32
TXPAUSE
Pause all SPIs transmit FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the SPI transmitters.
8
9
TXPAUSED
All SPI transmit FIFOs are paused.
9
10
FIFOCTLUSART
USART FIFO global control register. These registers are byte, halfword, and word addressable.The upper 16 bits of these registers provide information about the System FIFO configuration, and are specific to each device type.
0x100
read-write
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
8
RXEMPTY
All USART receive FIFOs are empty.
2
3
RXFIFOTOTAL
Reports the receive FIFO space available for USARTs on this FIFO. The reset value is device specific.
16
24
RXPAUSE
Pause all USARTs receive FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the USART receivers.
0
1
RXPAUSED
All USART receive FIFOs are paused.
1
2
TXEMPTY
All USART transmit FIFOs are empty.
10
11
TXFIFOTOTAL
Reports the transmit FIFO space available for USARTs on this FIFO. The reset value is device specific.
24
32
TXPAUSE
Pause all USARTs transmit FIFO operations. This can be used to prepare the System FIFO to reconfigure FIFO allocations among the USART transmitters.
8
9
TXPAUSED
All USART transmit FIFOs are paused.
9
10
FIFOUPDATESPI
SPI FIFO global update register
0x204
write-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
3
16
SPI0RXUPDATESIZE
Writing 1 updates SPI0 Rx FIFO size to match the SPI0 RXSIZE. Must be done for all SPIs when any SPI RXSIZE is changed.
0
1
SPI0TXUPDATESIZE
Writing 1 updates SPI0 Tx FIFO size to match the SPI0 TXSIZE. Must be done for all SPIs when any SPI TXSIZE is changed.
16
17
SPI1RXUPDATESIZE
Writing 1 updates SPI1 Rx FIFO size to match the SPI1 RXSIZE. Must be done for all SPIs when any SPI RXSIZE is changed.
1
2
SPI1TXUPDATESIZE
Writing 1 updates SPI1 Tx FIFO size to match the SPI1 TXSIZE. Must be done for all SPIs when any SPI TXSIZE is changed.
17
18
FIFOUPDATEUSART
USART FIFO global update register
0x104
write-only
n
0x0
0x0
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
16
RESERVED
Reserved. Read value is undefined, only zero should be written.
4
16
USART0RXUPDATESIZE
Writing 1 updates USART0 Rx FIFO size to match the USART0 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed.
0
1
USART0TXUPDATESIZE
Writing 1 updates USART0 Tx FIFO size to match the USART0 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed.
16
17
USART1RXUPDATESIZE
Writing 1 updates USART1 Rx FIFO size to match the USART1 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed.
1
2
USART1TXUPDATESIZE
Writing 1 updates USART1 Tx FIFO size to match the USART1 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed.
17
18
USART2RXUPDATESIZE
Writing 1 updates USART2 Rx FIFO size to match the USART2 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed.
2
3
USART2TXUPDATESIZE
Writing 1 updates USART2 Tx FIFO size to match the USART2 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed.
18
19
USART3RXUPDATESIZE
Writing 1 updates USART3 Rx FIFO size to match the USART3 RXSIZE. Must be done for all USARTs when any USART RXSIZE is changed.
3
4
USART3TXUPDATESIZE
Writing 1 updates USART3 Tx FIFO size to match the USART3 TXSIZE. Must be done for all USARTs when any USART TXSIZE is changed.
19
20
INTSTATSPI0
SPI0 interrupt status
0x4010
read-only
n
0x0
0x0
BUSERR
Bus Error. This is simply a copy of the same bit in the STATSPI register. The bus error interrupt is always enabled.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. This is simply a copy of the same field in the STATSPI register, included here so an ISR can read all needed status information in one read.
16
24
RXEMPTY
Receive FIFO Empty. This is simply a copy of the same bit in the STATSPI register.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled.
0
1
RXTIMEOUT
Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGSPI register, and the related interrupt is enabled.
4
5
TXCOUNT
Transmit FIFO Available. This is simply a copy of the same field in the STATSPI register, included here so an ISR can read all needed status information in one read.
24
32
TXEMPTY
Transmit FIFO Empty. This is simply a copy of the same bit in the STATSPI register.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled.
1
2
INTSTATSPI1
SPI0 interrupt status
0x6118
read-only
n
0x0
0x0
BUSERR
Bus Error. This is simply a copy of the same bit in the STATSPI register. The bus error interrupt is always enabled.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. This is simply a copy of the same field in the STATSPI register, included here so an ISR can read all needed status information in one read.
16
24
RXEMPTY
Receive FIFO Empty. This is simply a copy of the same bit in the STATSPI register.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled.
0
1
RXTIMEOUT
Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGSPI register, and the related interrupt is enabled.
4
5
TXCOUNT
Transmit FIFO Available. This is simply a copy of the same field in the STATSPI register, included here so an ISR can read all needed status information in one read.
24
32
TXEMPTY
Transmit FIFO Empty. This is simply a copy of the same bit in the STATSPI register.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled.
1
2
INTSTATUSART0
USART0 interrupt status
0x2010
read-only
n
0x0
0x0
BUSERR
Bus Error. This is simply a copy of the same bit in the STATUSART register. The bus error interrupt is always enabled.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
16
24
RXEMPTY
Receive FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled.
0
1
RXTIMEOUT
Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register, and the related interrupt is enabled.
4
5
TXCOUNT
Transmit FIFO Available. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
24
32
TXEMPTY
Transmit FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled.
1
2
INTSTATUSART1
USART0 interrupt status
0x3118
read-only
n
0x0
0x0
BUSERR
Bus Error. This is simply a copy of the same bit in the STATUSART register. The bus error interrupt is always enabled.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
16
24
RXEMPTY
Receive FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled.
0
1
RXTIMEOUT
Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register, and the related interrupt is enabled.
4
5
TXCOUNT
Transmit FIFO Available. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
24
32
TXEMPTY
Transmit FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled.
1
2
INTSTATUSART2
USART0 interrupt status
0x4320
read-only
n
0x0
0x0
BUSERR
Bus Error. This is simply a copy of the same bit in the STATUSART register. The bus error interrupt is always enabled.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
16
24
RXEMPTY
Receive FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled.
0
1
RXTIMEOUT
Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register, and the related interrupt is enabled.
4
5
TXCOUNT
Transmit FIFO Available. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
24
32
TXEMPTY
Transmit FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled.
1
2
INTSTATUSART3
USART0 interrupt status
0x5628
read-only
n
0x0
0x0
BUSERR
Bus Error. This is simply a copy of the same bit in the STATUSART register. The bus error interrupt is always enabled.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
16
24
RXEMPTY
Receive FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled.
0
1
RXTIMEOUT
Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register, and the related interrupt is enabled.
4
5
TXCOUNT
Transmit FIFO Available. This is simply a copy of the same field in the STATUSART register, included here so an ISR can read all needed status information in one read.
24
32
TXEMPTY
Transmit FIFO Empty. This is simply a copy of the same bit in the STATUSART register.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled.
1
2
RXDATSPI0
SPI0 received data. These registers are half word addressable.
0x4028
read-only
n
0x0
0x0
RESERVED
Reserved, the value read from a reserved bit is not defined.
21
32
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
17
RXSSEL1_N
Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
17
18
RXSSEL2_N
Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
18
19
RXSSEL3_N
Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
19
20
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
21
RXDATSPI1
SPI0 received data. These registers are half word addressable.
0x613C
read-only
n
0x0
0x0
RESERVED
Reserved, the value read from a reserved bit is not defined.
21
32
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
17
RXSSEL1_N
Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
17
18
RXSSEL2_N
Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
18
19
RXSSEL3_N
Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
19
20
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
21
RXDATSTATUSART0
USART0 received data with status
0x2030
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
15
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
RXNOISE
Received Noise flag.
15
16
RXDATSTATUSART1
USART0 received data with status
0x3148
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
15
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
RXNOISE
Received Noise flag.
15
16
RXDATSTATUSART2
USART0 received data with status
0x4360
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
15
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
RXNOISE
Received Noise flag.
15
16
RXDATSTATUSART3
USART0 received data with status
0x5678
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
14
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
15
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
13
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
RXNOISE
Received Noise flag.
15
16
RXDATUSART0
USART0 received data
0x2028
read-only
n
0x0
0x0
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
32
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
RXDATUSART1
USART0 received data
0x313C
read-only
n
0x0
0x0
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
32
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
RXDATUSART2
USART0 received data
0x4350
read-only
n
0x0
0x0
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
32
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
RXDATUSART3
USART0 received data
0x5664
read-only
n
0x0
0x0
RESERVED
Reserved, the value read from a reserved bit is not defined.
9
32
RXDAT
The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
0
9
STATSPI0
SPI0 status
0x4008
read-write
n
0x0
0x0
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for SPI. The bus error flag can be cleared by writing a 1 to this bit.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field.
16
24
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit.
0
1
RXTIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGSPI register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable.
4
5
TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled.
24
32
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit.
1
2
STATSPI1
SPI0 status
0x610C
read-write
n
0x0
0x0
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for SPI. The bus error flag can be cleared by writing a 1 to this bit.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field.
16
24
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit.
0
1
RXTIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGSPI register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable.
4
5
TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled.
24
32
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit.
1
2
STATUSART0
USART0 status
0x2008
read-write
n
0x0
0x0
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for USARTn. The bus error flag can be cleared by writing a 1 to this bit.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field.
16
24
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit.
0
1
RXTIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable.
4
5
TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled.
24
32
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit.
1
2
STATUSART1
USART0 status
0x310C
read-write
n
0x0
0x0
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for USARTn. The bus error flag can be cleared by writing a 1 to this bit.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field.
16
24
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit.
0
1
RXTIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable.
4
5
TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled.
24
32
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit.
1
2
STATUSART2
USART0 status
0x4310
read-write
n
0x0
0x0
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for USARTn. The bus error flag can be cleared by writing a 1 to this bit.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field.
16
24
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit.
0
1
RXTIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable.
4
5
TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled.
24
32
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit.
1
2
STATUSART3
USART0 status
0x5614
read-write
n
0x0
0x0
BUSERR
Bus Error. When 1, a bus error has occurred while processing data for USARTn. The bus error flag can be cleared by writing a 1 to this bit.
7
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
2
4
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RESERVED
Reserved. Read value is undefined, only zero should be written.
5
7
RXCOUNT
Receive FIFO Count. Indicates how many entries may be read from the receive FIFO. 0 = FIFO empty. This is a read-only field.
16
24
RXEMPTY
Receive FIFO Empty. When 1, the receive FIFO is currently empty. This is a read-only bit.
8
9
RXTH
Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached. This is a read-only bit.
0
1
RXTIMEOUT
Receive FIFO Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGUSART register. The timeout condition can be cleared by writing a 1 to this bit, by enabling or disabling the timeout interrupt, or by writing a 1 to the timeout interrupt enable.
4
5
TXCOUNT
Transmit FIFO Count. Indicates how many entries may be written to the transmit FIFO. 0 = FIFO full. This is a read-only field that is valid only when the TxFIFO is fully configured and enabled.
24
32
TXEMPTY
Transmit FIFO Empty. When 1, the transmit FIFO is currently empty. This is a read-only bit.
9
10
TXTH
Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached. This is a read-only bit.
1
2
TXDATSPI0
SPI0 transmit data. These registers are half word addressable.
0x4030
write-only
n
0x0
0x0
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
22
ENUM
DATA_NOT_EOF
Data not EOF. This piece of data transmitted is not
treated as the end of a frame.
0
DATA_EOF
Data EOF. This piece of data is treated as the end
of a frame, causing the FRAME_DELAY time to be inserted
before subsequent data is transmitted.
1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
21
ENUM
NOT_DEASSERTED
Not deasserted. SSEL not deasserted. This piece of
data is not treated as the end of a transfer. SSEL will not
be deasserted at the end of this data.
0
DEASSERTED
Deasserted. SSEL deasserted. This piece of data is
treated as the end of a transfer. SSEL will be deasserted at
the end of this piece of data.
1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential data transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
28
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process and can be used with the DMA.
22
23
ENUM
READ_RECEIVED_DATA
Read received data. Received data must be read in
order to allow transmission to progress. In slave mode, an
overrun error will occur if received data is not read before
new data is received.
0
IGNORE_RECEIVED_DATA
Ignore received data. Received data is ignored,
allowing transmission without reading unneeded received
data. No receiver flags are generated.
1
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register.
16
17
ENUM
ASSERTED
Asserted. SSEL0 asserted.
0
NOT_ASSERTED
Not asserted. SSEL0 not asserted.
1
TXSSEL1_N
Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register.
17
18
ENUM
ASSERTED
Asserted. SSEL1 asserted.
0
NOT_ASSERTED
Not asserted. SSEL1 not asserted.
1
TXSSEL2_N
Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register.
18
19
ENUM
ASSERTED
Asserted. SSEL2 asserted.
0
NOT_ASSERTED
Not asserted. SSEL2 not asserted.
1
TXSSEL3_N
Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register.
19
20
ENUM
ASSERTED
Asserted. SSEL3 asserted.
0
NOT_ASSERTED
Not asserted. SSEL3 not asserted.
1
TXDATSPI1
SPI0 transmit data. These registers are half word addressable.
0x6148
write-only
n
0x0
0x0
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
22
ENUM
DATA_NOT_EOF
Data not EOF. This piece of data transmitted is not
treated as the end of a frame.
0
DATA_EOF
Data EOF. This piece of data is treated as the end
of a frame, causing the FRAME_DELAY time to be inserted
before subsequent data is transmitted.
1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
21
ENUM
NOT_DEASSERTED
Not deasserted. SSEL not deasserted. This piece of
data is not treated as the end of a transfer. SSEL will not
be deasserted at the end of this data.
0
DEASSERTED
Deasserted. SSEL deasserted. This piece of data is
treated as the end of a transfer. SSEL will be deasserted at
the end of this piece of data.
1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential data transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
28
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
23
24
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process and can be used with the DMA.
22
23
ENUM
READ_RECEIVED_DATA
Read received data. Received data must be read in
order to allow transmission to progress. In slave mode, an
overrun error will occur if received data is not read before
new data is received.
0
IGNORE_RECEIVED_DATA
Ignore received data. Received data is ignored,
allowing transmission without reading unneeded received
data. No receiver flags are generated.
1
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register.
16
17
ENUM
ASSERTED
Asserted. SSEL0 asserted.
0
NOT_ASSERTED
Not asserted. SSEL0 not asserted.
1
TXSSEL1_N
Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register.
17
18
ENUM
ASSERTED
Asserted. SSEL1 asserted.
0
NOT_ASSERTED
Not asserted. SSEL1 not asserted.
1
TXSSEL2_N
Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register.
18
19
ENUM
ASSERTED
Asserted. SSEL2 asserted.
0
NOT_ASSERTED
Not asserted. SSEL2 not asserted.
1
TXSSEL3_N
Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register.
19
20
ENUM
ASSERTED
Asserted. SSEL3 asserted.
0
NOT_ASSERTED
Not asserted. SSEL3 not asserted.
1
TXDATUSART0
USART0 transmit data
0x2038
write-only
n
0x0
0x0
RESERVED
Reserved. Only zero should be written.
9
32
TXDAT
Writing to the UART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and the condition for transmitting data is met: TXDIS bit = 0.
0
9
TXDATUSART1
USART0 transmit data
0x3154
write-only
n
0x0
0x0
RESERVED
Reserved. Only zero should be written.
9
32
TXDAT
Writing to the UART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and the condition for transmitting data is met: TXDIS bit = 0.
0
9
TXDATUSART2
USART0 transmit data
0x4370
write-only
n
0x0
0x0
RESERVED
Reserved. Only zero should be written.
9
32
TXDAT
Writing to the UART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and the condition for transmitting data is met: TXDIS bit = 0.
0
9
TXDATUSART3
USART0 transmit data
0x568C
write-only
n
0x0
0x0
RESERVED
Reserved. Only zero should be written.
9
32
TXDAT
Writing to the UART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and the condition for transmitting data is met: TXDIS bit = 0.
0
9
WWDT
Windowed Watchdog Timer
WWDT
0x0
0x0
0x1000
registers
n
WDT
0
FEED
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.
0x8
write-only
n
0x0
0x0
FEED
Feed value should be 0xAA followed by 0x55.
0
8
RESERVED
Reserved. Read value is undefined, only zero should be written.
8
32
MOD
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
0x0
read-write
n
0x0
0x0
LOCK
Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset.
5
6
RESERVED
Reserved. Read value is undefined, only zero should be written.
6
32
WDEN
Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.
0
1
ENUM
STOP
Stop. The watchdog timer is stopped.
0
RUN
Run. The watchdog timer is running.
1
WDINT
Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.
3
4
WDPROTECT
Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
4
5
ENUM
FLEXIBLE
Flexible. The watchdog time-out value (TC) can be
changed at any time.
0
THRESHOLD
Threshold. The watchdog time-out value (TC) can be
changed only after the counter is below the value of
WDWARNINT and WDWINDOW.
1
WDRESET
Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
1
2
ENUM
INTERRUPT
Interrupt. A watchdog time-out will not cause a
chip reset.
0
RESET
Reset. A watchdog time-out will cause a chip
reset.
1
WDTOF
Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1.
2
3
TC
Watchdog timer constant register. This 24-bit register determines the time-out value.
0x4
read-write
n
0x0
0x0
COUNT
Watchdog time-out value.
0
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
32
TV
Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.
0xC
read-only
n
0x0
0x0
COUNT
Counter timer value.
0
24
RESERVED
Reserved. Read value is undefined, only zero should be written.
24
32
WARNINT
Watchdog Warning Interrupt compare value.
0x14
read-write
n
0x0
0x0
RESERVED
Reserved, only zero should be written.
10
32
WARNINT
Watchdog warning interrupt compare value.
0
10
WINDOW
Watchdog Window compare value.
0x18
read-write
n
0x0
0x0
RESERVED
Reserved, only zero should be written.
24
32
WINDOW
Watchdog window value.
0
24